Address decoding circuit, memory, and control method
AssigneeChangxin Memory Technologies, Inc.
InventorYinchuan Gu
Life of this patent
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Abstract
An address decoding circuit includes a decoding unit corresponding to a bank group and including first NAND gates, an address selection signal outputted by each first NAND gate controls a corresponding bank in the bank group corresponding to the decoding unit. The first NAND gate includes a first input end connected to an address signal of a bank corresponding to the first NAND gate and a second input end connected to an output end of a second NAND gate or a third NAND gate, the second NAND gate includes a first input end connected to an enable signal and a second input end connected to a control signal, and the third NAND gate includes a first input end connected to the enable signal and a second input end connected to an inverted signal of the control signal.
Claims14
An address decoding circuit, comprising:
- a plurality of decoding unit each corresponding to a bank group, wherein
- each decoding unit comprises a plurality of first Negated AND (NAND) gates, an address selection signal outputted by each first NAND gate is configured to control a corresponding bank in the bank group corresponding to the decoding unit, and the first NAND gate includes a first input end connected to an address signal of a bank corresponding to the first NAND gate and a second input end connected to an output end of a second NAND gate or an output end of a third NAND gate;
- the second NAND gate includes a first input end connected to an enable signal and a second input end connected to a control signal, and the third NAND gate includes a first input end connected to the enable signal and a second input end connected to an inverted signal of the control signal.
Dependencies are inferred from the claim text.