US 11,901,007 B2 · Positive TCO voltage to dummy select transistors in 3D memory

Abstract

Technology for applying a positive temperature coefficient (Tco) voltage to a control terminal of a dummy select transistor. The dummy select transistor resides on a NAND string having non-volatile memory cells and a regular select transistor. The dummy select transistor is typically ON (or conductive) during memory operations such as selected string program, read, and verify. In an aspect, the positive Tco voltage is applied to the control terminal of a dummy select transistor during a program operation. Applying the positive Tco voltage during program operations reduces or eliminates program disturb to the dummy select transistor. In some aspects, the dummy select transistor is used to generate a gate induced drain leakage (GIDL) current during an erase operation. In some aspects, the dummy select transistor is a depletion mode transistor.

Claims20

Dependent claims

A non-volatile storage apparatus, comprising:

a control circuit configured to connect to a three dimensional memory structure having a plurality of conductive lines and a plurality of NAND strings associated with the plurality of conductive lines, each NAND string comprising non-volatile storage cells and a dummy select gate and a regular select gate, each dummy select gate having a control terminal, wherein each dummy select gate is connected to one of the conductive lines, wherein the regular select gate is between the dummy select gate and the non-volatile storage cells of the NAND string;
wherein the control circuit is configured to:
determine a present temperature with respect to the three dimensional memory structure;
and
apply a voltage having a positive temperature coefficient to the control terminals of respective dummy select gates of a group of the NAND strings during a program operation.

2 more elements

A method of operating non-volatile storage, the method comprising:

determining a present temperature of a three-dimensional memory structure that comprises NAND strings, each NAND string comprising a depletion mode transistor, an enhancement mode select transistor, and non-volatile memory cells, the enhancement mode select transistor between the depletion mode transistor and the non-volatile memory cells of the NAND string;
and
applying a voltage to respective control terminals of the depletion mode transistors of a group of the NAND strings during a program operation, the voltage having a magnitude that depends positively on the present temperature of the three-dimensional memory structure.

A non-volatile storage system comprising:

a plurality of conductive lines;
a three-dimensional memory structure comprising a plurality of NAND strings and a plurality of word lines, each of the NAND strings comprising a plurality of non-volatile memory cells, a regular select transistor, and a gate induced drain leakage (GIDL) transistor at an end of the NAND string that is connected to one of the conductive lines, the regular select transistor between the GIDL transistor and the non-volatile memory cells of the NAND string;
and
a control circuit that:
applies a voltage between control terminals of respective GIDL transistors of a group of the NAND strings and the conductive lines at the end of the NAND strings having the respective GIDL transistors to generate gate induced drain leakage (GIDL) currents during an erase operation;
applies a program voltage to a selected word line connected to the group of NAND strings during a program operation;
and
applies a voltage that has a positive dependence on temperature to the control terminals of the respective GIDL transistors of the group of the NAND strings while the program voltage is applied to the selected word line during the program operation.

5 more elements

Dependencies are inferred from the claim text.

Positive TCO voltage to dummy select transistors in 3D memory

Life of this patent

Positive TCO voltage to dummy select transistors in 3D memory

Life of this patent

Abstract

Claims20