Apparatuses and methods for memory including ferroelectric memory cells and dielectric memory cells

An apparatus, comprising:

• a first memory cell comprising first and second dielectric capacitors configured to store first charges representing complementary logical values;
• a second memory cell comprising first and second ferroelectric capacitors configured to store second charges representing complementary logical values, both the first and second ferroelectric capacitors coupled to a first plate line;
• a first bit line selectably coupled to the first ferroelectric capacitor of the second memory cell and to the first dielectric capacitor of the first memory cell;
• and
• a second bit line selectably coupled to the second ferroelectric capacitor of the second memory cell and to the second dielectric capacitor of the first memory cell;
• a first word line selectably coupled to the first memory cell;
• and
• a second word line selectably coupled to the second memory cell,
• wherein, when the first and second word lines are driven to a same voltage, the first memory cell is further configured store the first charges to the first and second dielectric capacitors of the first memory cell and the second memory cell is configured to restore the second charges to the first and second ferroelectric capacitors.

An apparatus comprising:

• a processor configured to process memory access operations, the processor including a memory controller integrated therein;
• and
• a memory comprising:
• a first memory cell comprising first and second ferroelectric capacitors configured to store first charges that represent complementary logical values;
• a second memory cell comprising first and second dielectric capacitors configured to store second charges that represent complementary logical values;
• a first word line selectably coupled to the first memory cell;
• a second word line selectably coupled to the second memory cell;
• a first bit line selectably coupled to the first ferroelectric capacitor of the first memory cell and to the first dielectric capacitor of the second memory cell;
• and
• a second bit line selectably coupled to the second ferroelectric capacitor of the first memory cell and to the second dielectric capacitor of the second memory cell,
• wherein, when the first and second word lines are driven to a same voltage, the first memory cell is further configured store the first charges to the first and second ferroelectric capacitors of the first memory cell and the second memory cell is configured to restore the second charges to the first and second dielectric capacitors;
• and
• wherein the memory controller is configured to select the first and second bit lines.

A method, comprising:

• reading a data bit from a first memory cell that includes first and second dielectric capacitors configured to store first charges that represent complementary logical values;
• latching the data bit at a sense amplifier;
• writing the data bit from the sense amplifier back to the first memory cell, via a first bit line, to restore the charge that represents the data bit through the logical value;
• and
• while maintaining the charge that represents the data bit through the logical value at the first memory cell, writing the data bit from the sense amplifier to a second memory cell, via the first bit line, that includes first and second ferroelectric capacitors configured to store second charges that represent complementary logical values.