Memory array, memory structure and operation method of memory array

A memory structure, comprising:

• memory cells, formed on a substrate, and respectively comprising:
• a write transistor, disposed on a surface of the substrate;
• an electrically programmable non-volatile memory (NVM), disposed over the write transistor, wherein a first terminal of the electrically programmable NVM is electrically connected to a first source/drain structure of the write transistor, and a second terminal of the electrically programmable NVM is electrically connected to a bit line lying over the electrically programmable NVM;
• and
• a capacitor, disposed over the write transistor, with a bottom electrode electrically connected to the first terminal of the electrically programmable NVM and the first source/drain structure of the write transistor.

An operation method of a memory array, wherein the memory array comprises memory cells and floating gate transistors, the memory cells respectively comprise a capacitor, an electrically programmable non-volatile memory (NVM) serially connected to the capacitor and a write transistor coupled to a common node of the capacitor and the electrically programmable NVM, the floating gate transistor respectively have a gate terminal electrically floated and coupled to the capacitors of a column of the memory cells, and the operation method comprises:

• turning on the write transistors to program the electrically programmable NVMs with conductances indicating various weights stored in the memory cells;
• switching off the write transistors;
• and
• performing a matrix-vector multiplication (MVM) cycle, comprising:
• providing voltage pulses as inputs to the electrically programmable NVMs, wherein the inputs and the weights are multiplied at the memory cells and summed at the gate terminals of the floating gate transistors, and output currents as results of the MVM operation are output by the floating gate transistors;
• and
• discharging the capacitors.