Memory array with multiplexed digit lines
AssigneeMicron Technology, Inc.
InventorsFerdinando Bedeschi, Stefan Frederik Schippers
Life of this patent
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Abstract
Methods, systems, and devices for a memory device with multiplexed digit lines are described. In some cases, a memory cell of the memory device may include a storage component and a selection component that includes two transistors. A first transistor may be coupled with a word line and a second transistor may be coupled with a select line to selectively couple the memory cell with a digit line. The selection component, in conjunction with a digit line multiplexing component, may support a sense component common to a set of digit lines. In some cases, the digit line of the set may be coupled with the sense component during a read operation, while the remaining digit lines of the set are isolated from the sense component.
Claims12
A memory device, comprising:
- a substrate;
- and
- a memory cell comprising a storage component, a first vertical transistor, and a second vertical transistor,
- the first vertical transistor comprising a first gate coupled with a word line and a first doped region extending in a first direction away from a surface of the substrate;
- and
- the second vertical transistor comprising a second gate coupled with a select line and a second doped region extending in the first direction away from the surface of the substrate, the first vertical transistor is a first distance away from the substrate and the second vertical transistor is above the first vertical transistor a second distance away from the substrate different than the first distance, and the word line is a third distance away from the surface of the substrate and the select line is above the word line a fourth distance away from the surface of the substrate different than the third distance.
Dependencies are inferred from the claim text.