Electronic device related to a precharge operation
AssigneeSK hynix Inc.
InventorHaeng Seon Chae
Life of this patent
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Abstract
An electronic device may include: a clock divider circuit configured to generate a first internal clock including pulses which are generated in synchronization with odd pulses of a clock, and generate a second internal clock including pulses which are generated in synchronization with even pulses of the clock; and a command decoder configured to generate an odd precharge command and an even precharge command based on a counting signal which is toggled by a chip selection signal and a command/address signal for performing a precharge operation in synchronization with the first internal clock or toggled by the chip selection signal and the command/address signal for performing the precharge operation in synchronization with the second internal clock.
Claims20
An electronic device comprising:
- a clock divider circuit configured to:
- generate a first internal clock including pulses which are generated in synchronization with odd pulses of a clock, and
- generate a second internal clock including pulses which are generated in synchronization with even pulses of the clock;
- and
- a command decoder configured to generate an odd precharge command and an even precharge command based on a counting signal which is toggled by a chip selection signal and a command and address (command/address) signal for performing a precharge operation in synchronization with the first internal clock or toggled by the chip selection signal and the command/address signal for performing the precharge operation in synchronization with the second internal clock,
- wherein the command decoder is configured to:
- generate a pulse of the odd precharge command as a pulse corresponding to two or more periods of the clock, and
- generate a pulse of the even precharge command as a pulse corresponding to two or more periods of the clock.
An electronic device comprising:
- a command decoder configured to generate an odd precharge command and an even precharge command based on a counting signal which is toggled by a chip selection signal and a command and address (command/address) signal for performing a first precharge operation and a second precharge operation in synchronization with a first internal clock or toggled by the chip selection signal and the command/address signal for performing the first and second precharge operations in synchronization with a second internal clock;
- and
- a core circuit configured to:
- perform the first precharge operation on banks at the same positions, which are included in a first bank group and a second bank group, according to an internal address signal generated from the command/address signal when any one of the odd precharge command and the even precharge command is input, or
- perform the second precharge operation on one of a plurality of banks included in the first and second bank groups according to the internal address signal generated from the command/address signal when any one of the odd precharge command and the even precharge command is input,
- wherein the command decoder is configured to:
- generate a pulse of the odd precharge command as a pulse corresponding to two or more periods of a clock, and
- generate a pulse of the even precharge command as a pulse corresponding to two or more periods of the clock.
Dependencies are inferred from the claim text.