Semiconductor memory device with a plurality of memory units

A semiconductor memory device comprising:

• a plurality of memory units arranged in a first direction;
• a plurality of first semiconductor layers arranged in the first direction and electrically connected to the plurality of memory units;
• a plurality of first gate electrodes arranged in the first direction and opposed to the plurality of first semiconductor layers;
• a first wiring extending in the first direction and connected to the plurality of first semiconductor layers;
• a plurality of second wirings arranged in the first direction, extending in a second direction intersecting with the first direction, and connected to the plurality of first gate electrodes;
• a plurality of second semiconductor layers arranged in the first direction and disposed at first end portions in the second direction of the plurality of second wirings;
• a plurality of second gate electrodes arranged in the first direction and opposed to the plurality of second semiconductor layers;
• a plurality of third semiconductor layers arranged in the first direction and disposed at second end portions in the second direction of the plurality of second wirings;
• and
• a plurality of third gate electrodes arranged in the first direction and opposed to the plurality of third semiconductor layers.