Display substrate having a scan driving circuit with a plurality of shift registers and manufacturing method thereof, display device

A display substrate, comprising:

• a base substrate, comprising a pixel array region and a peripheral region;
• and
• a first scan driving circuit, a plurality of power lines, a first signal line group, and a second signal line group, which are in the peripheral region and located on a first side of the base substrate,
• wherein the first scan driving circuit comprises a plurality of cascaded first shift registers;
• the plurality of power lines are configured to provide a plurality of power voltages to the plurality of cascaded first shift registers in the first scan driving circuit;
• the first signal line group comprises at least one timing signal line configured to provide at least one timing signal to the plurality of cascaded first shift registers in the first scan driving circuit;
• the second signal line group comprises a first trigger signal line configured to be connected to a first-stage first shift register of the plurality of cascaded first shift registers in the first scan driving circuit and to provide a first trigger signal to the first-stage first shift register;
• both the plurality of power lines and the first signal line group are between the second signal line group and the pixel array region;
• the plurality of power lines comprise a first power line and a second power line, and
• the first power line and the second power line are configured to provide a same first power voltage.

A display substrate, comprising:

• a base substrate, comprising a pixel array region and a peripheral region;
• and
• a first scan driving circuit, a plurality of power lines, a first signal line group, and a second signal line group, which are in the peripheral region and located on a first side of the base substrate,
• wherein the first scan driving circuit comprises a plurality of cascaded first shift registers;
• the plurality of power lines are configured to provide a plurality of power voltages to the plurality of cascaded first shift registers in the first scan driving circuit;
• the first signal line group comprises at least one timing signal line configured to provide at least one timing signal to the plurality of cascaded first shift registers in the first scan driving circuit;
• the second signal line group comprises a first trigger signal line configured to be connected to a first-stage first shift register of the plurality of cascaded first shift registers in the first scan driving circuit and to provide a first trigger signal to the first-stage first shift register;
• both the plurality of power lines and the first signal line group are between the second signal line group and the pixel array region;
• the plurality of power lines comprise a first power line and a second power line,
• the first power line and the second power line are configured to provide a same first power voltage;
• an orthographic projection of the first power line on the base substrate partially overlaps with an orthographic projection of the first scan driving circuit on the base substrate;
• and
• an orthographic projection of the second power line on the base substrate is between the orthographic projection of the first power line on the base substrate and an orthographic projection of the second signal line group on the base substrate.