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US 11,900,868 B2Granted
Display panel and display device
AssigneeWuhan Tianma Microelectronics Co., Ltd.
InventorDian Zhang
Life of this patent
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Abstract
Provided are a display panel and a display device. The display panel includes multiple pixel units, multiple scan lines, multiple data lines, a multiplexer and h control signal lines. In a same data write stage of the display panel, during a first stage, data signals are written into the multiple data lines at an enable duration of a j-th control signal, during a second stage, a first scan enable voltage edge of an i-th scan signal is located behind a first control enable voltage edge of the j-th control signal, and the data signals on the multiple data lines are written into the multiple pixel units; and a second scan enable voltage edge of the i-th scan signal in a m-th data write stage is located before a second control enable voltage edge of an n-th control signal in a (m+1)-th data write stage.
Claims20
A display panel, comprising:
- a plurality of pixel units;
- a plurality of scan lines, wherein the plurality of scan lines comprise an i-th scan line, the i-th scan line is configured to transmit an i-th scan signal to pixel units arranged in a row along a first direction, the i-th scan signal comprises a first scan enable voltage edge and a second scan enable voltage edge in sequence, a time duration between the first scan enable voltage edge and the second scan enable voltage edge is an enable duration of the i-th scan signal, wherein i is a positive integer;
- a plurality of data lines, wherein the plurality of data lines are configured to transmit data signals to pixel units arranged in a column along a second direction, and comprise first data lines and second data lines, the first data lines are electrically connected to pixel units of odd-numbered rows in a column of pixel units among the plurality of pixel units, the second data lines are electrically connected to pixel units of even-numbered rows in a column of pixel units among the plurality of pixel units, and the first direction intersects with the second direction;
- a multiplexer, wherein the multiplexer comprises a plurality of selector output terminals and a plurality of selector control terminals, and each of the plurality of selector output terminals is electrically connected to a respective one of the plurality of data lines;
- and
- h control signal lines, wherein each of the h control signal lines is electrically connected to a respective one of the plurality of selector control terminals, and the h control signal lines comprise a j-th control signal line, the j-th control signal line is configured to transmit a j-th control signal, the j-th control signal comprises a first control enable voltage edge and a second control enable voltage edge in sequence, a time duration between the first control enable voltage edge and the second control enable voltage edge is an enable duration of the j-th control signal, wherein 1≤j≤h, and j and h are positive integers,
- wherein a drive timing of the display panel comprises a data write stage, and the data write stage comprises a first stage and a second stage,
- wherein in a same data write stage, during the first stage, the data signals are written into the plurality of data lines at the enable duration of the j-th control signal, during the second stage, the first scan enable voltage edge of the i-th scan signal is located behind the first control enable voltage edge of the j-th control signal, and the data signals on the plurality of data lines are written into the plurality of pixel units, and
- wherein the second scan enable voltage edge of the i-th scan signal in a m-th data write stage is located before a second control enable voltage edge of an n-th control signal in a (m+1)-th data write stage, wherein |n−j|<h, 1≤n≤h, and m and n are positive integers.
6 more elements
A display device, comprising a display panel,
- wherein the display panel comprises:
- a plurality of pixel units;
- a plurality of scan lines, wherein the plurality of scan lines comprise an i-th scan line, the i-th scan line is configured to transmit an i-th scan signal to pixel units arranged in a row along a first direction, the i-th scan signal comprises a first scan enable voltage edge and a second scan enable voltage edge in sequence, a time duration between the first scan enable voltage edge and the second scan enable voltage edge is an enable duration of the i-th scan signal, wherein i is a positive integer;
- a plurality of data lines, wherein the plurality of data lines are configured to transmit data signals to pixel units arranged in a column along a second direction, and comprise first data lines and second data lines, the first data lines are electrically connected to pixel units of odd-numbered rows in a column of pixel units among the plurality of pixel units, the second data lines are electrically connected to pixel units of even-numbered rows in a column of pixel units among the plurality of pixel units, and the first direction intersects with the second direction;
- a multiplexer, wherein the multiplexer comprises a plurality of selector output terminals and a plurality of selector control terminals, and each of the plurality of selector output terminals is electrically connected to a respective one of the plurality of data lines;
- and
- h control signal lines, wherein each of the h control signal lines is electrically connected to a respective one of the plurality of selector control terminals, and the h control signal lines comprise a j-th control signal line, the j-th control signal line is configured to transmit a j-th control signal, the j-th control signal comprises a first control enable voltage edge and a second control enable voltage edge in sequence, a time duration between the first control enable voltage edge and the second control enable voltage edge is an enable duration of the j-th control signal, wherein 1≤j≤h, and j and h are positive integers,
- wherein a drive timing of the display panel comprises a data write stage, and the data write stage comprises a first stage and a second stage,
- wherein in a same data write stage, during the first stage, the data signals are written into the plurality of data lines at the enable duration of the j-th control signal, during the second stage, the first scan enable voltage edge of the i-th scan signal is located behind the first control enable voltage edge of the j-th control signal, and the data signals on the plurality of data lines are written into the plurality of pixel units, and
- wherein the second scan enable voltage edge of the i-th scan signal in a m-th data write stage is located before a second control enable voltage edge of an n-th control signal in a (m+1)-th data write stage, wherein |n−j|<h, 1≤n≤h, and m and n are positive integers.
7 more elements
Dependencies are inferred from the claim text.