Computer-implemented method, apparatus, and computer-program product

An apparatus, comprising:

• a memory;
• and
• one or more processors;
• wherein the memory and the one or more processors are connected with each other;
• and
• the memory stores computer-executable instructions for controlling the one or more processors to:
• input a low-resolution image into a generator;
• and
• generate a high-resolution image using the generator based on the low-resolution image by processing the low-resolution image through a plurality of super-resolution generating units arranged in series in the generator;
• wherein a respective output from a respective one of the plurality of super-resolution generating units has a respective increased image resolution as compared to a respective input to the respective one of the plurality of super-resolution generating units;
• wherein the respective one of the plurality of super-resolution generating units comprises a super-resolution generating block and a bilinear interpolation block;
• wherein the memory further stores computer-executable instructions for controlling the one or more processors to:
• input a respective input to the super-resolution generating block and the bilinear interpolation block, respectively;
• process the respective input using the super-resolution generating block to generate a first intermediate output from the super-resolution generating block;
• input the first intermediate output from the super-resolution generating block to the bilinear interpolation block;
• and
• generate a second intermediate output using the bilinear interpolation block based on the respective input and the first intermediate output;
• wherein the super-resolution generating block comprises a plurality of encoding modules and a plurality of decoding modules arranged in a u-net architecture;
• a respective one of the plurality of encoding modules comprises a down-sampling convolutional layer, and a plurality of first residual blocks arranged in series;
• and
• a respective one of the plurality of decoding modules comprises a plurality of second residual blocks arranged in series, and an up-sampling convolutional layer.

A computer-program product comprising a non-transitory tangible computer-readable medium having computer-readable instructions thereon, the computer-readable instructions being executable by a processor to cause the processor to perform:

• inputting a low-resolution image into a generator;
• and
• generating a high-resolution image using the generator based on the low-resolution image;
• wherein generating the high-resolution image comprises processing the low-resolution image through a plurality of super-resolution generating units arranged in series in the generator, wherein a respective output from a respective one of the plurality of super-resolution generating units has a respective increased image resolution as compared to a respective input to the respective one of the plurality of super-resolution generating units;
• wherein the respective one of the plurality of super-resolution generating units comprises a super-resolution generating block and a bilinear interpolation block;
• wherein generating the high-resolution image using the generator further comprises:
• inputting a respective input to the super-resolution generating block and the bilinear interpolation block, respectively;
• processing the respective input using the super-resolution generating block to generate a first intermediate output from the super-resolution generating block;
• inputting the first intermediate output from the super-resolution generating block to the bilinear interpolation block;
• and
• generating a second intermediate output using the bilinear interpolation block based on the respective input and the first intermediate output;
• wherein the super-resolution generating block comprises a plurality of encoding modules and a plurality of decoding modules arranged in a u-net architecture;
• a respective one of the plurality of encoding modules comprises a down-sampling convolutional layer, and a plurality of first residual blocks arranged in series;
• and
• a respective one of the plurality of decoding modules comprises a plurality of second residual blocks arranged in series, and an up-sampling convolutional layer.