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US 11,900,539 B2Granted
Tile sequencing mechanism
AssigneeIntel Corporation
InventorsSubramaniam Maiyuran, Saurabh Sharma, Jorge F. Garcia Pabon, Raghavendra Kamath Miyar, Sudheendra Srivathsa, Justin Decell, Aditya Navale
Life of this patent
Estimating the term…
Abstract
An apparatus to facilitate graphics rendering is disclosed. The apparatus comprises sequencer hardware to operate in a tile mode to render objects, including performing batch formation to generate one or more batches of received objects, performing tile sequencing for each of the objects to compute tile fill intersects for each of the objects and performing a play sequencing of each of the objects.
Claims20
An apparatus comprising:
- a graphics processor including graphics processing resources configured for tile-based immediate-mode rendering, the graphics processor including:
- a cache memory to store object data and associated control data for objects to be rendered by the graphics processor;
- and
- sequencer circuitry to:
- generate a plurality of batches of the objects to be rendered, each of the plurality of batches sized according to a size of the cache memory,
- determine tiles intersected by objects in each of the plurality of batches,
- maintain lit transaction information for the plurality of batches based on the intersected tiles, and
- perform a play sequencing of each of the objects based on the lit transaction information,
- wherein to perform the play sequencing includes to:
- select, based on the lit transaction information, a cache aware tile-walk pattern;
- and
- walk lit tiles according to the tile-walk pattern, wherein to walk a lit tile includes to process primitive commands for objects in the plurality of batches of objects that are associated with the lit tile.
9 more elements
A method comprising:
- rendering objects on a graphics processor that is configured in a tile-based immediate render mode, including:
- generating a plurality of batches of objects to be rendered, each of the plurality of batches sized according to a size of a cache memory of the graphics processor;
- determining tiles intersected by objects in each of the plurality of batches;
- maintaining lit transaction information for the plurality of batches based on the intersected tiles;
- and
- performing a play sequencing of each of the objects based on the lit transaction information, wherein object data and associated control data are stored to the cache memory of the graphics processor for use during play sequencing, wherein performing the play sequencing includes:
- selecting, based on the lit transaction information, a cache aware tile-walk pattern;
- and
- walking lit tiles according to the tile-walk pattern, wherein to walk a lit tile includes to process primitive commands for objects in the plurality of batches of objects that are associated with the lit tile.
6 more elements
A graphics processing unit (GPU), comprising:
- a cache memory to store object data and associated control data for objects to be rendered via tile-based immediate-mode rendering;
- sequencer circuitry to:
- generate a plurality of batches of objects to be rendered, each of the plurality of batches sized according to a size of a cache memory of the graphics processing unit;
- determine tiles intersected by objects in each of the plurality of batches;
- maintain lit transaction information for the plurality of batches based on the intersected tiles;
- perform a play sequencing of each of the objects based on the lit transaction information, wherein object data and associated control data are stored to the cache memory for use during play sequencing;
- and
- rasterization circuitry to rasterize the objects into pixel data based on the play sequencing, wherein to perform the play sequencing includes to select, based on the lit transaction information, a cache aware tile-walk pattern and walk lit tiles according to the tile-walk pattern, wherein to walk a lit tile includes to process primitive commands for objects in the plurality of batches of objects that are associated with the lit tile.
5 more elements
Dependencies are inferred from the claim text.