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US 11,900,242 B2Granted
Integrated circuit chip apparatus
AssigneeCambricon Technologies Corporation Limited
InventorsShaoli Liu, Xinkai Song, Bingrui Wang, Yao Zhang, Shuai Hu
Life of this patent
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Abstract
Provided are an integrated circuit chip apparatus and a related product, the integrated circuit chip apparatus being used for executing a multiplication operation, a convolution operation or a training operation of a neural network. The present technical solution has the advantages of a small amount of calculation and low power consumption.
Claims20
An integrated circuit chip apparatus, comprising:
- a main processing circuit;
- and
- a plurality of basic processing circuits arranged in a form of an array, wherein the main processing circuit is connected to k basic processing circuits of the plurality of basic processing circuits arranged on one or more sides of the array,
- wherein the main processing circuit is configured to transfer data and a computation instruction to the k basic processing circuits, wherein the data comprises a broadcast data block and a plurality of basic data blocks partitioned from a data block to be computed,
- wherein to transfer the data to the k basic processing circuits, the main processing circuit is further configured to:
- distribute the plurality of basic data blocks to the k basic processing circuits;
- and
- broadcast the broadcasting data block to the k basic processing circuits,
- wherein the k basic processing circuits are configured to forward data received from the main processing circuit to the other basic processing circuits among the plurality of basic processing circuits,
- wherein the plurality of basic processing circuits are configured to perform a first set of neural network computations in parallel on the data transferred, and transfer computation results to the main processing circuit through the k basic processing circuits,
- wherein the main processing circuit is further configured to perform a second set of neural network computations in series on the computation results.
8 more elements
A processing system, comprising:
- a neural network computing apparatus;
- a general interconnection interface;
- and
- a general-purpose processing apparatus connected to the neural network computing apparatus via the general interconnection interface,
- wherein the neural network computing apparatus further comprises:
- a main processing circuit;
- and
- a plurality of basic processing circuits arranged in a form of an array, wherein the main processing circuit is connected to k basic processing circuits of the plurality of basic processing circuits arranged on one or more sides of the array,
- wherein the main processing circuit is configured to transfer data and a computation instruction to the k basic processing circuits, wherein the data comprises a broadcast data block and a plurality of basic data blocks partitioned from a data block to be computed,
- wherein to transfer the data to the k basic processing circuits, the main processing circuit is further configured to:
- distribute the plurality of basic data blocks to the k basic processing circuits;
- and
- broadcast the broadcasting data block to the k basic processing circuits,
- wherein the k basic processing circuits are configured to forward data received from the main processing circuit to the other basic processing circuits among the plurality of basic processing circuits,
- wherein the plurality of basic processing circuits are configured to perform a first set of neural network computations in parallel on the data transferred, and transfer computation results to the main processing circuit through the k basic processing circuits,
- wherein the main processing circuit is further configured to perform a second set of neural network computations in series on the computation results.
13 more elements
A method for performing neural network operations using an integrated circuit chip apparatus comprising a main processing circuit, and a plurality of basic processing circuits arranged in a form of an array, wherein the main processing circuit is connected to k basic processing circuits of the plurality of basic processing circuits arranged on one or more sides of the array, the method comprising:
- transferring data and a computation instruction from the main processing circuit to the k basic processing circuits, wherein the data comprises a broadcast data block and a plurality of basic data blocks partitioned from a data block to be computed, wherein transferring the data to the k basic processing circuits further comprises:
- distributing the plurality of basic data blocks to the k basic processing circuits;
- and
- broadcasting the broadcasting data block to the k basic processing circuits;
- forwarding, by the k basic processing circuits, data received from the main processing circuit to the other basic processing circuits among the plurality of basic processing circuits;
- performing, by the plurality of basic processing circuits, a first set of neural network computations in parallel on the data forwarded;
- transferring the computation results to the main processing circuit through the k basic processing circuits;
- and
- performing, by the main processing circuit, a second set of neural network computations in series on the computation results.
6 more elements
Dependencies are inferred from the claim text.