Improving memory access handling for nested virtual machines

A system, comprising:

• a memory;
• a processing device operatively coupled to the memory, the processing device configured to:
• running a Level 0 hypervisor managing a Level 1 virtual machine running a Level 1 hypervisor, wherein the Level 1 hypervisor manages a Level 2 virtual machine, wherein the Level 2 virtual machine is associated with a Peripheral Component Interconnect (PCI) device;
• assign an input/output (I/O) virtual address space to be used by the PCI device;
• receive, from the Level 1 hypervisor, a guest page table maintained by the Level 1 hypervisor;
• generate a Level 1 page table by combining records from the guest page table with records from a host page table maintained by the Level 0 hypervisor;
• cause a central processing unit (CPU) of a host computer system to use the Level 1 page table for first level address translations;
• generate a Level 2 page table comprising a plurality of Level 2 page table entries, wherein each Level 2 page table entry of the plurality of Level 2 page table entries maps a I/O guest virtual address of the I/O virtual address space to a corresponding Level 2 guest physical address;
• and
• cause a device driver of the Level 2 virtual machine to use the Level 2 page table for second level address translation.

A non-transitory machine-readable storage medium storing instructions that cause a processing device to:

• running a Level 0 hypervisor managing a Level 1 virtual machine running a Level 1 hypervisor, wherein the Level 1 hypervisor manages a Level 2 virtual machine, wherein the Level 2 virtual machine is associated with a Peripheral Component Interconnect (PCI) device;
• assign an input/output (I/O) virtual address space to be used by the PCI device;
• receive, from the Level 1 hypervisor, a guest page table maintained by the Level 1 hypervisor;
• generate a Level 1 page table by combining records from the guest page table with records from a host page table maintained by the Level 0 hypervisor;
• cause a central processing unit (CPU) of a host computer system to use the Level 1 page table for first level address translations;
• generate a Level 2 page table comprising a plurality of Level 2 page table entries, wherein each Level 2 page table entry of the plurality of Level 2 page table entries maps a I/O guest virtual address of the I/O virtual address space to a corresponding Level 2 guest physical address;
• and
• cause a device driver of the Level 2 virtual machine to use the Level 2 page table for second level address translation.