Memory-network processor with programmable optimizations

A method, comprising:

• fetching, by a fetch unit of a processor, a multi-part instruction from an instruction stream, wherein the multi-part instruction includes a plurality of fields;
• generating, by a first address generator unit of the processor based on a first field of the multi-part instruction, an address from which to retrieve first data to be stored in a first register for use by an execution unit for the multi-part instruction or a subsequent multi-part instruction;
• generating by a second address generator unit of the processor based on a second field of the multi-part instruction, an address from which to retrieve second data to be stored in a second register for use by an execution unit for the multi-part instruction or a subsequent multi-part instruction;
• performing a first operation that operates on operands from a plurality of registers, by one or more execution units, using a first pipeline of a plurality of pipelines, based on a third field of the plurality of fields;
• and
• performing a second operation that operates on operands from a plurality of registers, by one or more execution units, using at least two pipelines of the plurality of pipelines in parallel, based on a fourth field of the plurality of fields, wherein performing the second operation using the at least two pipelines in parallel comprises generating, by a second pipeline of the at least two pipelines, a first set of partial products and generating, by a third pipeline of the at least two pipelines, a second set of partial products dependent upon at least one partial product of the first set of partial products.

A non-transitory computer-readable medium having instructions stored thereon that are executable by a computing device to perform operations comprising:

• fetching a multi-part instruction from an instruction stream, wherein the multi-part instruction includes a plurality of fields;
• generating, based on a first field of the multi-part instruction, an address from which to retrieve first data to be stored in a first register for use by an execution unit for the multi-part instruction or a subsequent multi-part instruction;
• generating, based on a second field of the multi-part instruction, an address from which to retrieve second data to be stored in a second register for use by an execution unit for the multi-part instruction or a subsequent multi-part instruction;
• performing a first operation that operates on operands from a plurality of registers, based on a third field of the plurality of fields;
• and
• performing a second operation that operates on operands from a plurality of registers using at least two pipelines of a plurality of pipelines in parallel, based on a fourth field of the plurality of fields, wherein performing the second operation using the at least two pipelines in parallel comprises generating, by a first pipeline of the at least two pipelines, a first set of partial products and generating, by a second pipeline of the at least two pipelines, a second set of partial products dependent upon at least one partial product of the first set of partial products.