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US 11,900,112 B2Granted
Vector reverse
AssigneeTexas Instruments Incorporated
InventorsTimothy D. Anderson, Duc Bui
Life of this patent
Estimating the term…
Abstract
A method to reverse source data in a processor in response to a vector reverse instruction includes specifying, in respective fields of the vector reverse instruction, a source register containing the source data and a destination register. The source register includes a plurality of lanes and each lane contains a data element, and the destination register includes a plurality of lanes corresponding to the lanes of the source register. The method further includes executing the vector reverse instruction by creating reversed source data by reversing the order of the data elements, and storing the reversed source data in the destination register.
Claims20
A processor comprising:
- an instruction fetch unit configured to receive a vector reverse instruction that specifies a single vector reverse operation;
- and
- a datapath coupled to the instruction fetch unit that includes:
- a global register file that includes a source register including a set of n lanes configured to store a first vector that includes a set of n elements, in which a first element of the set of n elements is stored in a first lane of the set of n lanes and each succeeding element of the set of n elements is stored in a respective succeeding lane of the set of n lanes, and a destination register including a set of n lanes respectively corresponding to the set of n lanes of the source register, wherein n is an integer of 4 or greater;
- and
- a set of functional units coupled to the global register file that includes a first functional unit, wherein:
- the vector reverse instruction specifies the first functional unit from among the set of functional units;
- and
- the first functional unit is configured to, based on the vector reverse instruction:
- receive the first vector from the source register;
- reverse an order of the set of n elements of the first vector to produce a second vector;
- and
- cause the second vector to be stored in the destination register, in which a first element of the second vector is stored in the nth lane of the destination register and each of succeeding element of the second vector is stored in a respective preceding lane of the destination register,
- wherein the vector reverse instruction is completed in a single operation.
11 more elements
A processor comprising:
- an instruction fetch unit configured to receive a vector reverse instruction and a second instruction, wherein the vector reverse instruction specifies whether the processor is to perform the vector reverse instruction and the second instruction in parallel and further specifies that the vector reverse instruction is a single vector reverse operation;
- a register file that includes a source register configured to store a first vector that includes a set of elements stored in a first order and a destination register;
- a functional unit coupled to the register file and configured to, based on the vector reverse instruction:
- receive the first vector from the source register;
- reverse an order of the set of elements of the first vector to produce a second vector that includes all elements of the set of elements;
- and
- cause all elements of the second vector to be stored in the destination register in a second order that is reverse of the first order,
- wherein the vector reverse instruction is completed in a single operation.
5 more elements
A method comprising:
- receiving a vector reverse instruction that specifies a source register in a register file, a destination register in the register file, and a functional unit from among a set of functional units, wherein the source register includes a set of n lanes and the destination register includes a set of n lanes respectively corresponding to the set of n lanes of the source register, wherein n is an integer of 4 or greater, wherein the vector reverse instructions further specifies that the vector reverse instruction is a single vector reverse operation;
- and
- based on the vector reverse instruction, performing, by the specified functional unit:
- receiving a first vector from the source register, wherein the first vector includes a set of n elements, in which a first element of the set of n elements is stored in a first lane of the set of n lanes in the source register and each succeeding element of the set of n elements is stored in a respective succeeding lane of the set of n lanes in the source register;
- reversing the set of elements of the first vector to produce a second vector;
- and
- storing the second vector in the destination register, in which a first element of the second vector is stored in the nth lane of the destination register and each of succeeding element of the second vector is stored in a respective preceding lane of the destination register,
- wherein the vector reverse instruction is completed in a single operation.
5 more elements
Dependencies are inferred from the claim text.