Instructions for fused multiply-add operations with variable precision input operands

A method comprising:

• fetching a fused multiply-accumulate (FMA) instruction having a plurality of fields usable to identify an opcode, a first input value, a second input value, and a third input value, wherein the first and the second input values each comprise first and second sets of vector data elements, respectively, wherein each of the vector data elements of at least the second set of vector data elements has an M-bit width, wherein the third input value comprises an N-bit accumulation value, where N is an integer multiple of M;
• decoding the FMA instruction;
• and
• executing, by a single instruction multiple data (SIMD) execution circuit, the FMA instruction in an N-bit SIMD lane, wherein executing comprises multiplying each data element of the second set of vector data elements by a corresponding data element of the first set of vector data elements to produce a plurality of temporary products, and adding the temporary products to the N-bit accumulation value to produce an N-bit result value;
• wherein the N-bit SIMD lane is one of a 16-bit lane, a 32-bit lane, and a 64-bit lane, and the M-bit width comprises one of a 4-bit width and an 8-bit width, and
• the SIMD execution circuit comprises a first SIMD execution circuit and the N-bit SIMD lane comprises a first N-bit SIMD lane, the method further comprising executing, by a second SIMD execution circuit, the FMA instruction in a second N-bit SIMD lane.

A machine-readable medium having program code stored thereon which, when executed by a machine, causes the machine to perform operations of:

• fetching a fused multiply-accumulate (FMA) instruction having a plurality of fields usable to identify an opcode, a first input value, a second input value, and a third input value, wherein the first and the second input values each comprise first and second sets of vector data elements, respectively, wherein each of the vector data elements of at least the second set of vector data elements has an M-bit width, wherein the third input value comprises an N-bit accumulation value, where N is an integer multiple of M;
• decoding the FMA instruction;
• and
• executing, by a single instruction multiple data (SIMD) execution circuit, the FMA instruction in an N-bit SIMD lane, wherein executing comprises multiplying each data element of the second set of vector data elements by a corresponding data element of the first set of vector data elements to produce a plurality of temporary products, and adding the temporary products to the N-bit accumulation value to produce an N-bit result value;
• wherein the N-bit SIMD lane is one of a 16-bit lane, a 32-bit lane, and a 64-bit lane, and the M-bit width comprises one of a 4-bit width and an 8-bit width, and
• the SIMD execution circuit comprises a first SIMD execution circuit and the N-bit SIMD lane comprises a first N-bit SIMD lane, the machine-readable medium further comprising program code to cause the machine to perform the operations of executing, by a second SIMD execution circuit, the FMA instruction in a second N-bit SIMD lane.