Simulation method and device, power wire topology network, test circuit and storage medium

A simulation device, comprising a memory and a processor;

• wherein the memory is configured to store an executable instruction of the processor;
• wherein the processor is configured to:
• generate a power wire topology network according to a power wire layout, wherein the power wire topology network comprises a plurality of first layer of metal wires arranged in a transverse direction, a plurality of second layer of metal wires arranged in a longitudinal direction, power child nodes and a parasitic element, and the parasitic element is located between two power child nodes;
• determine a minimum voltage of a power input node of each circuit module in a circuit corresponding to the power wire topology network, and the power input node is one of the power child nodes in each circuit module;
• perform a time sequence simulation according to the minimum voltage of the power input node of each circuit module and the post-simulation circuit network list of an integrated circuit, wherein the post-stimulation circuit network list of the integrated circuit does not comprise a parasitic capacitance or a parasitic resistance;
• and
• perform post-stimulation by using the parasitic capacitance and the parasitic resistance after the time sequence simulation is completed.