Methods and systems for verifying a property of an integrated circuit hardware design using a quiescent state

A computer-implemented method of verifying a property of an integrated circuit hardware design, the method comprising, at one or more processors:

• formally verifying, using a formal verification tool, that the property is true for the hardware design under a constraint that an instantiation of the hardware design transitions to a quiescent state at a symbolic time;
• wherein formally verifying that the property is true for the hardware design under a constraint that an instantiation of the hardware design transitions to a quiescent state at a symbolic time comprises:
• linking, to the hardware design, one or more assertions which set out the property to be verified,
• receiving quiescent logic configured to implement the constraint, the quiescent logic comprising trigger logic configured to detect a quiescent trigger that occurs at a symbolic time, and transition logic configured to, in response to the trigger logic detecting the quiescent trigger, cause the instantiation of the hardware design to transition to a quiescent state, and
• linking the quiescent logic to the hardware design prior to formally verifying that the one or more assertions are true for the hardware design.