Method and system to abort a command for PCIe based non-volatile memory express solid-state drive

A system for aborting a command for a Peripheral Component Interconnect express (PCIe) based Non-Volatile Memory express (NVMe) Solid-State Drive (SSD), the system comprising:

• a processor;
• and
• a memory communicatively coupled to the processor,
• wherein the memory stores processor-executable instructions, which on execution, cause the processor to:
• receive an abort command in an Admin submission queue of a host to abort a target command in an Input/Output (I/O) submission queue of the host or in an I/O queue of the NVMe SSD, wherein the abort command comprises slot information of the target command to be aborted;
• update a tail doorbell of NVMe doorbell registers of the NVMe SSD after receiving the abort command in the Admin submission queue;
• place the abort command into an Admin queue of the NVMe SSD after updating the tail doorbell of the NVMe doorbell registers by the host;
• execute the abort command, wherein the execute comprises:
• determining whether the target command has been received in the NVMe SSD;
• aborting the target command in response to determining that the target command has been received in the NVMe SSD;
• using the slot information of the target command to be aborted for updating an I/O completion queue of the host with the target command to be aborted in response to determining that the target command has not been received;
• update a head doorbell of the NVMe doorbell registers of the NVMe SSD after completing execution of the abort command;
• and
• placing information in an Admin completion queue of the host after the update of the head doorbell that indicates the aborting of the target command has completed.

A method for aborting a command for a Peripheral Component Interconnect express (PCIe) based Non-Volatile Memory express (NVMe) Solid-State Drive (SSD), the method comprising:

• receiving, by a host, an abort command in an Admin submission queue of the host to abort a target command scheduled to be performed on the NVMe SSD, wherein the abort command comprises information indicating whether the target command is located in a first queue of the host or a second queue of the NVMe SSD;
• updating, by the host, a first register of the NVMe SSD after receiving the abort command in the Admin submission queue;
• placing, by the NVMe SSD, the abort command into an Admin queue of the NVMe SSD after determining that the first register has been updated;
• determining, by the NVMe SSD, a selected queue among the first and second queues from the information;
• executing, by the NVMe SSD, the abort command, where the executing comprises:
• aborting, by the NVMe SSD, the target command in response to determining the selected queue is the second queue;
• updating an input/output (I/O) completion queue of the host to indicate the target command of the selected queue has been completed in response to determining the selected queue is the first queue;
• updating, by the host, a head doorbell of NVMe doorbell registers of the NVMe SSD after completing execution of the abort command by the NVMe SSD;
• and
• placing, by the NVMe SSD, information in an Admin completion queue of the host after the updating of the head doorbell that indicates the aborting of the target command has completed.