Method and apparatus for performing automatic setting control of memory device in predetermined communications architecture with aid of auxiliary setting management

A memory device, comprising:

• a non-volatile (NV) memory, arranged to store information, wherein the NV memory comprises at least one NV memory element;
• and
• a memory controller, coupled to the NV memory, arranged to control operations of the memory device, wherein the memory controller comprises:
• a processing circuit, arranged to control the memory controller according to a plurality of host commands from a host device, to allow the host device to access the NV memory through the memory controller;
• a transmission interface circuit, arranged to perform communications with the host device;
• and
• a hardware control circuit, arranged to perform automatic setting control of the memory device;
• wherein:
• during initialization of the memory device, the memory controller utilizes the processing circuit within the memory controller to load an auxiliary setting management table from the NV memory into at least one storage unit of the hardware control circuit within the memory controller to be a loaded auxiliary setting management table, wherein the hardware control circuit is used for the automatic setting control;
• and
• the memory controller utilizes the hardware control circuit within the memory controller to detect occurrence of a series of events according to state information of the transmission interface circuit within the memory controller, and to dynamically perform parameter setting on the transmission interface circuit according to the series of events, for reconfiguring the transmission interface circuit at runtime of the memory device, wherein the transmission interface circuit is reconfigured with data carried by one or more entries among multiple entries of the loaded auxiliary setting management table;
• wherein the transmission interface circuit comprises at least one state register circuit, wherein multiple register values of the at least one state register circuit are used as an indicator of any possible event among all possible events;
• and the hardware control circuit is arranged to detect the occurrence of the series of events through the at least one state register circuit, wherein the state information represents the multiple register values of the at least one state register circuit.

A memory controller of a memory device, the memory device comprising the memory controller and a non-volatile (NV) memory, the NV memory comprising at least one NV memory element, the memory controller comprising:

• a processing circuit, arranged to control the memory controller according to a plurality of host commands from a host device, to allow the host device to access the NV memory through the memory controller;
• a transmission interface circuit, arranged to perform communications with the host device;
• and
• a hardware control circuit, arranged to perform automatic setting control of the memory device;
• wherein:
• during initialization of the memory device, the memory controller utilizes the processing circuit within the memory controller to load an auxiliary setting management table from the NV memory into at least one storage unit of the hardware control circuit within the memory controller to be a loaded auxiliary setting management table, wherein the hardware control circuit is used for the automatic setting control;
• and
• the memory controller utilizes the hardware control circuit within the memory controller to detect occurrence of a series of events according to state information of the transmission interface circuit within the memory controller, and to dynamically perform parameter setting on the transmission interface circuit according to the series of events, for reconfiguring the transmission interface circuit at runtime of the memory device, wherein the transmission interface circuit is reconfigured with data carried by one or more entries among multiple entries of the loaded auxiliary setting management table;
• wherein the transmission interface circuit comprises at least one state register circuit, wherein multiple register values of the at least one state register circuit are used as an indicator of any possible event among all possible events;
• and the hardware control circuit is arranged to detect the occurrence of the series of events through the at least one state register circuit, wherein the state information represents the multiple register values of the at least one state register circuit.