Strategic power mode transition in a multi-memory device

An apparatus, comprising:

• a non-volatile memory;
• a volatile memory configured to operate as a cache for the non-volatile memory;
• and
• an interface controller coupled with the non-volatile memory and the volatile memory, the interface controller operable to cause the apparatus to:
• receive, from a host device, a command indicating that the apparatus is to transition from a power state in which the apparatus operates the volatile memory in a power mode for the volatile memory and the non-volatile memory in a power mode for the non-volatile memory;
• transition, based at least in part on the command, the volatile memory from the power mode for the volatile memory to an idle power mode for the volatile memory that consumes more power than the power mode for the volatile memory;
• transition, based at least in part on the command, the non-volatile memory from the power mode for the non-volatile memory to a first idle power mode for the non-volatile memory that consumes more power than the power mode for the volatile memory and that consumes less power than a second idle power mode for the non-volatile memory;
• determine that data associated with an access command from the host device is stored in the non-volatile memory based at least in part on determining that the data associated with the access command from the host device is not stored in the volatile memory, wherein a quantity of commands queued for the non-volatile memory is increased based at least in part on the determination;
• determine that the quantity of commands queued for the non-volatile memory has increased from a first quantity to a second quantity;
• and
• transition the non-volatile memory from the first idle power mode to the second idle power mode or an active mode that consumes more power than the second idle power mode based at least in part on determining that the quantity of commands queued for the non-volatile memory has increased from the first quantity to the second quantity.

An apparatus, comprising:

• a non-volatile memory comprising one or more clocks, one or more command and address buffers, and one or more memory banks;
• a volatile memory configured to operate as a cache for the non-volatile memory;
• and
• an interface controller coupled with the non-volatile memory and the volatile memory, the interface controller operable to cause the apparatus to:
• receive, from a host device, a command indicating that the apparatus is to transition from a power state in which the apparatus operates the volatile memory in a power mode for the volatile memory and the non-volatile memory in a power mode for the non-volatile memory;
• transition, based at least in part on the command, the volatile memory from the power mode for the volatile memory to an idle power mode for the volatile memory;
• and
• transition, based at least in part on the command, the non-volatile memory from the power mode for the non-volatile memory to an idle power mode for the non-volatile memory, wherein the transition is delayed until after receipt of an access command, from the host device, associated with data stored in the non-volatile memory instead of the volatile memory, wherein the one or more clocks and the one or more command and address buffers are powered up in the idle power mode and the one or more memory banks are powered down in the idle power mode.

An apparatus, comprising:

• a non-volatile memory;
• a volatile memory configured to operate as a cache for the non-volatile memory;
• and
• an interface controller coupled with the non-volatile memory and the volatile memory, the interface controller operable to cause the apparatus to:
• receive, from a host device, a command indicating that the apparatus is to transition from a power state in which the apparatus operates the volatile memory in a power mode for the volatile memory and the non-volatile memory in a power mode for the non-volatile memory;
• transition, based at least in part on the command, the volatile memory from the power mode for the volatile memory to an idle power mode for the volatile memory;
• transmit, to the host device based at least in part on the command, an indication of a delay for the host device to observe between communicating the command and communicating an access command, wherein the idle power mode for the volatile memory is associated with the delay;
• and
• transition, based at least in part on the command, the non-volatile memory from the power mode for the non-volatile memory to an idle power mode for the non-volatile memory, wherein the transition is delayed until after receipt of an access command, from the host device, associated with data stored in the non-volatile memory instead of the volatile memory.

A method performed by a memory device, comprising:

• receiving, from a host device, a command indicating that the memory device is to transition from a power state in which the memory device operates a volatile memory in a power mode for the volatile memory and a non-volatile memory in a power mode for the non-volatile memory, wherein the non-volatile memory comprises one or more clocks, one or more command and address buffers, and one or more memory banks;
• transitioning, based at least in part on the command, the volatile memory from the power mode for the volatile memory to an idle power mode for the volatile memory that consumes more power than the power mode for the volatile memory;
• and
• transitioning, based at least in part on the command, the non-volatile memory from the power mode for the non-volatile memory to a first idle power mode for the non-volatile memory that consumes more power than the power mode for the volatile memory and that consumes less power than a second idle power mode for the non-volatile memory, wherein the one or more clocks, the one or more command and address buffers, and the one or more memory banks are powered down in the first idle power mode, and wherein the one or more clocks and the one or more command and address buffers are powered up in the second idle power mode and the one or more memory banks are powered down in the second idle power mode.

A method performed by a memory device, comprising:

• receiving, from a host device, a command indicating that the memory device is to transition from a power state in which the memory device operates a volatile memory in a power mode for the volatile memory and a non-volatile memory in a power mode for the non-volatile memory;
• transitioning, based at least in part on the command, the volatile memory from the power mode for the volatile memory to an idle power mode for the volatile memory;
• transmitting, to the host device based at least in part on the command, an indication of a delay for the host device to observe between communicating the command and communicating an access command, wherein the idle power mode for the volatile memory is associated with the delay;
• and
• transitioning, based at least in part on the command, the non-volatile memory from the power mode for the non-volatile memory to an idle power mode for the non-volatile memory, wherein the transition is delayed until after receipt of an access command, from the host device, associated with data stored in the non-volatile memory instead of the volatile memory.