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US 11,899,936 B2Granted
Data transmission circuit, method and storage device
AssigneeChangxin Memory Technologies, Inc.
InventorsEnpeng Gao, Kangling Ji, Zengquan Wu
Life of this patent
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Abstract
This application relates to a data transmission circuit, a method, and a storage device. The data transmission circuit includes a delay module and a mode register data processing unit. The delay module delays a first preset time when receiving a mode register read command, and generates delayed read command. The mode register data processing unit is connected to the delay module, and reads setting parameters from the mode register in response to the mode register read command, and outputs the setting parameters in response to the delayed read command.
Claims13
A data transmission method, comprising:
- generating a delayed read command based on a delay module responding to a mode register read command, wherein an operation delay of the delay module is the first preset time, wherein the delay module comprise a first delay unit, a second delay unit, and a third delay unit;
- responding to the mode register read command, and reading setting parameters from the mode register based on a mode register data processing unit;
- wherein the mode register data processing unit outputs the setting parameters, in response to the delayed read command;
- generating, by the first delay unit of the delay module, a first delayed read command after a second preset time delay, when the mode register read command is received;
- generating, by the second delay unit of the delay module, a second delayed read command after a third preset time delay when the first delayed read command is received, and wherein the third preset time equals to an operation delay of a column selection control module;
- and
- generating, by the third delay unit of the delay module, a third delayed read command after a fourth preset time delay, when the second delayed read command is received;
- wherein generating by the third delay unit of the delay module further comprises:
- generating, by a first sub-delay unit of the third delay unit of the delay module, a third delayed read command after a fifth preset time delay, when the second delayed read command is received, wherein the fifth preset time is equal to an operation delay of a read-write amplifier;
- and
- generating, by a second sub-delay unit of the third delay unit of the delay module, a first delayed read command after a sixth preset time, when the third delayed read command is received, wherein, a sum of the fifth preset time and the sixth preset time is equal to the fourth preset time;
- wherein, a sum of the second preset time, the third preset time, and the fourth preset time is equal to the first preset time.
9 more elements
A data transmission circuit, comprising:
- a delay module generating a delayed read command after a first preset time delay when a mode register read command is received;
- and
- a mode register data processing unit, connecting to the delay module, wherein the mode register data processing unit reads setting parameters from the mode register in response to the mode register read command, and outputs the setting parameters in response to the delayed read command;
- wherein the delay module comprise:
- a first delay unit;
- a second delay unit, which is connected to an output terminal of the first delay unit;
- and
- a third delay unit, which is connected to an output terminal of the second delay unit and an input terminal of the mode register data processing unit;
- wherein the first delay unit generates a first delayed read command after a second preset time delay, when the mode register read command is received;
- wherein the second delay unit generates a second delayed read command after a third preset time delay when the first delayed read command is received, and wherein the third preset time equals to an operation delay of a column selection control module;
- wherein the third delay unit comprises:
- a first sub-delay unit, which is connected to the output terminal of the second delay unit;
- and
- a second sub-delay unit, which is connected to an output terminal of the first sub-delay unit and the input terminal of the mode register data processing unit,
- wherein the first sub-delay unit generates a third delayed read command after a fifth preset time delay, when the second delayed read command is received, wherein the fifth preset time is equal to an operation delay of a read-write amplifier;
- wherein the second sub-delay unit delays a sixth preset time and then generates the delayed read command when the third delayed read command is received;
- wherein, a sum of the fifth preset time and the sixth preset time is equal to the fourth preset time;
- wherein the third delay unit delays a fourth preset time and generates the third delayed read command, when the second delayed read command is received;
- and
- wherein, a sum of the second preset time, the third preset time, and the fourth preset time is equal to the first preset time.
17 more elements
A data transmission circuit, comprising:
- a delay module generating a delayed read command after a first preset time delay when a mode register read command is received;
- a mode register data processing unit, connecting to the delay module, wherein the mode register data processing unit reads setting parameters from the mode register in response to the mode register read command, and outputs the setting parameters in response to the delayed read command;
- a command decoding circuit, wherein a first output terminal of the command decoding circuit is connected to an input terminal of the delay module and an input terminal of the mode register data processing unit, wherein the command decoding circuit receives a read command, decodes the read command, and determines whether the read command is the mode register read command;
- when the read command is the mode register read command, the command decoding circuit outputs the mode register read command, otherwise, the command decoding circuit generates an array area data read command;
- and
- a data processing unit of the array area, wherein an input terminal of the data processing unit of the array area is connected to a second output terminal of the command decoding circuit and a storage unit array, wherein the data processing unit of the array area reads an array area data from the storage unit array in response to the array area data read command;
- wherein a difference between an operation delay of the data processing unit in the array area and the first preset time is a preset threshold.
4 more elements
Dependencies are inferred from the claim text.