Instruction based control of memory attributes

A graphics processor comprising:

• a processing resource including a graphics engine;
• a memory device;
• a first cache coupled with the processing resource and the memory device;
• and
• circuitry to process a memory access message received from the processing resource, the memory access message to access data of the memory device on behalf of the graphics engine, wherein to process the memory access message, the circuitry is configured to:
• determine whether the memory access message includes a first cache attribute, the first cache attribute to indicate whether the data is cacheable within the first cache;
• determine whether state information associated with the data includes a second cache attribute, the second cache attribute to indicate whether the data is cacheable within the first cache;
• arbitrate between the first cache attribute and the second cache attribute according to presence or absence of the first cache attribute and the second cache attribute and respective priorities associated with the first cache attribute and the second cache attribute;
• and
• transmit a memory access request to the first cache, the memory access request including arbitrated cache attributes.