Method and apparatus to process an instruction for a distributed logic having tightly coupled accelerator core and processor core in a multi-dimensional packaging

A method of processing an instruction for a distributed logic having an accelerator core and a processor core that are tightly coupled in a multi-dimensional packaging configuration, the method comprising:

• fetching the instruction;
• determining whether a type of the instruction is for the processor core or for the accelerator core, wherein the processor core is part of a compute die while the accelerator core is part of an accelerator die, wherein the processor core is coupled to a first memory, wherein the accelerator core is coupled to a second memory, wherein the processor core and/or the accelerator core includes ferroelectric logic;
• assembling the instruction in a command packet that includes data address associated with the second memory;
• and
• sending the command packet to the accelerator core via an interconnect.

A system comprising:

• a memory to store one or more instructions;
• a processor circuitry coupled to the memory, the processor circuitry to execute one or more instructions, the processor circuitry comprising a plurality of processor cores, wherein the processor circuitry is on a compute die;
• and
• an accelerator circuitry coupled the processor circuitry, wherein the accelerator circuitry includes a plurality of accelerator cores, wherein:
• an individual processor core is tightly coupled to an individual accelerator core via an interconnect,
• the accelerator circuitry is on an accelerator die,
• the compute die and the accelerator die are in a 3D or 2.5D package configuration;
• the individual processor core is coupled to a first memory,
• the individual accelerator core is coupled to a second memory,
• the individual processor core is to fetch an instruction and to determine whether the instruction is to be scheduled for processing by the individual processor core or the individual accelerator core based on a type of the instruction, and
• the individual processor core is to assemble the instruction in a command packet that includes data address associated with the second memory, and to send the command packet to the individual accelerator core via the interconnect.