Method and apparatus for providing C-PHY interface via FPGA IO interface

A method for providing a C physical layer (“C-PHY”) input output (“IO”) interface via a field programmable gate arrays (“FPGA”), comprising:

• coupling a first wire of data lane 0 to a first terminal of first IO serializer of FPGA for receiving first data from a D physical layer (“D-PHY”) transmitter of a first device;
• coupling a second wire of the data lane 0 to a second terminal of the first IO serializer of FPGA for receiving second data from the D-PHY transmitter;
• activating a first low-voltage differential signaling (“LVDS”) to generate a first value on P channel of the first LVDS and a second value on N channel of the LVDS in response to the first data and the second data;
• and
• generating a first signal on first wire of trio 0 for a C-PHY output based on the first value on the P channel of the first LVDS.

An interface bridging device for converting data formatted in D physical layer (“D-PHY”) to data formatted in C physical layer (“C-PHY”), comprising;

• a D-PHY receiving block, operated by a first programmed portion of programmable logic elements (“LEs”) of field programmable gate arrays (“FPGA”), configured to receive incoming data from a plurality of lanes based on D-PHY protocol;
• a display serial interface (“DSI”) D-PHY decoder, operated by a second programmed portion of programmable LEs of FPGA, coupled to the D-PHY receiving block and configured to generate decoded data in accordance with the incoming data;
• a storage block coupled to the DSI D-PHY decoder and configured to temporarily buffer the decoded data;
• and
• a DSI C-PHY encoder coupled to the storage block and configured to generating values in C-PHY protocol by encoding the decoded data.