Apparatuses, methods, and systems for hardware control of processor performance levels

A system comprising:

• memory to store an operating system to execute on a processor;
• and
• the processor comprising:
• a decoder to decode instructions;
• an execution unit to execute the decoded instructions;
• and
• a plurality of registers, comprising:
• a first register to indicate capabilities values of processor performance levels,
• a second register to indicate whether one or more of performance status changes have occurred, including whether a change to highest performance has occurred, and
• a third register to indicate whether one or more interrupts are to be generated upon the performance status changes, including whether an interrupt is to be generated when the change to highest performance occurs, wherein the third register includes a first single bit that when set, is to indicate that the interrupt is to be generated when the change to the highest performance occurs, wherein the third register includes a second single bit that when set, is to indicate that one interrupt is to be generated when an excursion to a minimum performance occurs, and wherein the third register further includes a third single bit that when set, is to indicate that one interrupt is to be generated when a change to a guaranteed performance occurs.

A method comprising:

• decoding instructions by a decoder of a processor;
• executing the decoded instructions by an execution unit of the processor;
• indicating, by a first register of a plurality of registers, capabilities values of processor performance levels;
• indicating, by a second register of the plurality of registers, whether one or more of performance status changes have occurred, including whether a change to highest performance has occurred;
• and
• indicating, by a third register of the plurality of registers, whether one or more interrupts are to be generated upon the performance status changes, including whether an interrupt is to be generated when the change to highest performance occurs wherein the third register includes a first single bit that when set, is to indicate that the interrupt is to be generated when the change to the highest performance occurs, wherein the third register includes a second single bit that when set, is to indicate that one interrupt is to be generated when an excursion to a minimum performance occurs, and wherein the third register further includes a third single bit that when set, is to indicate that one interrupt is to be generated when a change to a guaranteed performance occurs.