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US 11,899,586 B1Granted
Energy efficient tag partitioning in cache memory
AssigneeSynopsys, Inc.
InventorKarthik Thucanakkenpalayam Sundararajan
Life of this patent
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Abstract
A memory address may be received at an m-way set-associative cache, which may store a set of cache entries. The memory address may be partitioned into a tag, an index, and an offset. The m-way set-associative cache may include a first structure to store a first subset of tag bits corresponding to the set of cache entries and a second structure to store a second subset of tag bits corresponding to the set of cache entries. The index may be used to select a first set of entries from the first structure. A first portion of tag bits of the memory address may be matched with the first set of entries. A cache status may be determined based on matching the first portion of tag bits of the memory address with the first set of entries.
Claims20
A method, comprising:
- receiving a memory address at an m-way set-associative cache, wherein the memory address is partitioned into a tag, an index, and an offset, wherein the m-way set-associative cache stores a set of cache entries, and wherein the m-way set-associative cache includes a first structure to store a first subset of tag bits corresponding to the set of cache entries and a second structure to store a second subset of tag bits corresponding to the set of cache entries;
- using the index to select m entries in the first structure;
- matching a first portion of tag bits of the memory address with the m entries in the first structure;
- and
- in response to the first portion of tag bits of the memory address matching n entries in the first structure, where n is less than m, matching a second portion of tag bits of the memory address with n entries in the second structure corresponding to the n entries in the first structure;
- and
- wherein the matching the first portion of tag bits of the memory address with the m entries in the first structure and the matching the second portion of tag bits of the memory address with n entries in the second structure is performed in a single clock cycle.
4 more elements
An integrated circuit (IC), comprising:
- a first circuit to store a set of cache entries, wherein each cache entry includes one or more words of data, wherein each word of data corresponds to a memory address, and wherein the memory address is partitioned into a tag, an index, and an offset;
- a first structure to store a first subset of tag bits corresponding to the set of cache entries;
- a second structure to store a second subset of tag bits corresponding to the set of cache entries;
- and
- a second circuit to:
- use the index to select m entries in the first structure;
- match a first portion of tag bits of the memory address with the m entries in the first structure;
- in response to the first portion of tag bits of the memory address matching n entries in the first structure, where n is less than m, match a second portion of tag bits of the memory address with n entries in the second structure corresponding to the n entries in the first structure;
- and
- wherein the matching the first portion of tag bits of the memory address with the m entries in the first structure and the matching the second portion of tag bits of the memory address with n entries in the second structure is performed in a single clock cycle.
7 more elements
An apparatus, comprising:
- a processor;
- a main memory;
- and
- a m-way set-associative cache coupled to the processor and the main memory, the m-way set-associative cache comprising:
- a first circuit to store a set of cache entries, wherein each cache entry includes one or more words of data, wherein each word of data corresponds to a memory address, and wherein the memory address is partitioned into a tag, an index, and an offset;
- a first structure to store a first subset of tag bits corresponding to the set of cache entries;
- a second structure to store a second subset of tag bits corresponding to the set of cache entries;
- and
- a second circuit to:
- use the index to select m entries in the first structure;
- match a first portion of tag bits of the memory address with the m entries in the first structure by matching each bit of the first portion of tag bits with a corresponding bit of each entry in the m entries in the first structure;
- in response to the first portion of tag bits of the memory address matching n entries in the first structure, where n is less than m, match a second portion of tag bits of the memory address with n entries in the second structure corresponding to the n entries in the first structure;
- and
- wherein the matching the first portion of tag bits of the memory address with the m entries in the first structure and the matching the second portion of tag bits of the memory address with n entries in the second structure is performed in a single clock cycle.
11 more elements
Dependencies are inferred from the claim text.