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US 11,899,583 B2Granted
Multi-dimensional cache architecture
AssigneeArm Limited
InventorsJoshua Randall, Alejandro Rico Carro, Dam Sunwoo, Saurabh Pijuskumar Sinha, Jamshed Jalal
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Abstract
Various implementations described herein are directed to a device with a multi-layered logic structure with multiple layers including a first layer and a second layer arranged vertically in a stacked configuration. The device may have a first cache memory with first interconnect logic disposed in the first layer. The device may have a second cache memory with second interconnect logic disposed in the second layer, wherein the second interconnect logic in the second layer is linked to the first interconnect logic in the first layer.
Claims20
A device comprising:
- a multi-layered logic structure with multiple layers including a first layer and a second layer arranged vertically in a stacked configuration, wherein:
- the first layer includes core processing logic and a first cache memory with first interconnect logic and a first router, wherein the core processing logic includes L1 cache memory disposed in the first layer,
- the second layer includes a second cache memory with second interconnect logic and a second router,
- the second interconnect logic in the second layer is linked to the first interconnect logic in the first layer with a first data link, and
- the second router in the second layer is linked to the first router in the first layer with a second data link that is different than the first data link.
2 more elements
A device comprising:
- a multi-layered logic structure having multiple layers that are arranged vertically in a stacked configuration;
- core processing logic and L1 cache memory disposed in a first layer of the multiple layers;
- an L2 cache memory split into multiple portions linked together with a first inter-layer data link, wherein a first portion of the L2 cache memory is disposed in a second layer of the multiple layers, and wherein a second portion of the L2 cache memory is disposed in a third layer of the multiple layers;
- and
- a routing network having at least one router disposed in each layer of the multiple layers including a first router disposed in the first layer with the L1 cache memory, second router disposed in the second layer with the first portion of L2 cache memory, and a third router disposed in the third layer with the second portion of L2 cache memory,
- wherein the second router is linked to the first router with a second inter-layer data link that is different than the first inter-layer data link, and
- wherein the third router is linked to the first router and the second router with the second inter-layer data link that is different than the first inter-layer data link.
4 more elements
A device comprising:
- a multi-layered logic structure with multiple layers including a first layer and a second layer arranged vertically in a stacked configuration;
- a first inter-layer data routing network having interconnect logic in each layer of the multiple layers including first interconnect logic in the first layer and second interconnect logic in the second layer that is linked to the first interconnect logic by way of the first inter-layer data routing network;
- a second inter-layer data routing network having at least one router in each layer of the multiple layers including a first router in the first layer and a second router in the second layer that is linked to the first router by way of the second inter-layer data routing network that is different than the first inter-layer data routing network;
- a first logic block disposed in the first layer, wherein the first logic block includes first core processing logic, first L2 cache memory and the first interconnect logic;
- and
- a second logic block disposed in the second layer, wherein the second logic block includes second core processing logic, second L2 cache memory and the second interconnect logic,
- wherein the first inter-layer data routing network includes first inter-layer data paths that vertically couple the interconnect logic in each layer together including the first interconnect logic in the first layer to the second interconnect logic in the second layer by way of the first inter-layer data routing network, and
- wherein the second inter-layer data routing network includes second inter-layer data paths that vertically couple the at least one router in each layer together including the first router in the first layer to the second router in the second layer by way of the second inter-layer data routing network, which is different than the first inter-layer data routing network that is different than the first inter-layer data routing network.
5 more elements
Dependencies are inferred from the claim text.