US 11,899,574 B2Granted

L2P translation techniques in limited RAM systems to increase random write performance using multiple L2P caches

AssigneeMicron Technology, Inc.

InventorsXiangang Luo, Qing Liang

Life of this patent

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Abstract

Devices and techniques are disclosed herein for more efficiently performing random write operation for a memory device. In an example, a method of operating a flash memory device can include receiving a write request at a flash memory device from a host, the write request including a first logical block address and write data, saving the write data to a location of the flash memory device having a first physical address, operating the flash memory device in a first mode when an amount of write data associated with the write request is above a threshold, operating the flash memory device in a second mode when an amount of write data is below the threshold, and comparing the amount of write data to the threshold.

Claims20

Dependent claims

A memory system, comprising:

a controller, configured to perform operations comprising:
receive a write request;
responsive to receiving the write request, compare an amount of data to be written in the write request to a threshold amount of data;
responsive to a determination that the amount of data to be written in the write request exceeds the threshold amount of data, storing a mapping between a physical and logical address corresponding to the write request in a first cache, the first cache configured to store, in a volatile memory, contiguous portions of a logical-to-physical mapping table indexed by logical block address;
responsive to a determination that the amount of data to be written in the write request does not exceed the threshold amount of data, storing the mapping in a second cache, the second cache configured to store, in a volatile memory, non-contiguous portions of the logical-to-physical mapping table indexed by logical block address;
determine if the second cache is full;
and
in response to a determination that the second cache is full:
determine if a first logical block address of the second cache is present in the first cache;
in response to a determination that the first logical block address of the second cache is present in the first cache:
store a first physical address associated with the first logical block address of the second cache with the first logical block address in the first cache;
and
mark a record with the first logical block address in the second cache as invalid.

10 more elements

A non-transitory, machine-readable medium, storing instructions, which when executed by a machine, causes the machine to perform operations comprising:

receive a write request;
responsive to receiving the write request, compare an amount of data to be written in the write request to a threshold amount of data;
responsive to a determination that the amount of data to be written in the write request exceeds the threshold amount of data, storing a mapping between a physical and logical address corresponding to the write request in a first cache, the first cache configured to store, in a volatile memory, contiguous portions of a logical-to-physical mapping table indexed by logical block address;
responsive to a determination that the amount of data to be written in the write request does not exceed the threshold amount of data, storing the mapping in a second cache, the second cache configured to store, in a volatile memory, non-contiguous portions of the logical-to-physical mapping table indexed by logical block address;
determine if the second cache is full;
and
in response to a determination that the second cache is full:
determine if a first logical block address of the second cache is present in the first cache;
in response to a determination that the first logical block address of the second cache is present in the first cache:
store a first physical address associated with the first logical block address of the second cache with the first logical block address in the first cache;
and
mark a record with the first logical block address in the second cache as invalid.

9 more elements

A method comprising:

receive a first write request;
responsive to receiving the first write request, compare an amount of data to be written in the first write request to a threshold amount of data;
responsive to a determination that the amount of data to be written in the first write request exceeds the threshold amount of data, storing a mapping between a physical and logical address corresponding to the first write request in a first cache, the first cache configured to store, in a volatile memory, contiguous portions of a logical-to-physical mapping table indexed by logical block address;
receiving a second write request;
responsive to receiving the second write request, compare an amount of data to be written in the second write request to the threshold amount of data;
responsive to a determination that the amount of data to be written in the second write request does not exceed the threshold amount of data, storing a mapping between a physical and logical address corresponding to the second write request in a second cache, the second cache configured to store, in a volatile memory, non-contiguous portions of the logical-to-physical mapping table indexed by logical block address;
determine if the second cache is full;
and
in response to a determination that the second cache is full:
determine if a first logical block address of the second cache is present in the first cache;
in response to a determination that the first logical block address of the second cache is present in the first cache:
store a first physical address associated with the first logical block address of the second cache with the first logical block address in the first cache;
and
mark a record with the first logical block address in the second cache as invalid.

11 more elements

Dependencies are inferred from the claim text.

Facts

Application: 17/965,542Filed 13 Oct 2022 · continuation
Priority: 27 Sep 2019
Published: US 2023/0031365 A12 Feb 2023
Granted: 13 Feb 2024
Term ends: Not estimatedThe source records don’t support an estimate.

Classification8 codes

G06F 12/0246
Memory management in non-volatile memory, e.g. resistive RAM or ferroelectric memory: in block erasable memory, e.g. flash memory
G06F 12/0804
Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches: with main…
G06F 12/0873
For peripheral storage systems, e.g. disk cache: mapping of cache memory to specific storage devices or parts thereof
G06F 12/1054
Associated with a data cache: the data cache being concurrently physically addressed

Family

Application16/586,519Parent of this continuation · filed 27 Sep 2019
US 2023/0031365 A1Pre-grant publication · published 2 Feb 2023
US 11,487,653 B2Parent of this continuation
US 2021/0096984 A1Published application
US 11,899,574 B2This patent

From the US filing history. Foreign family members aren’t listed.