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US 11,899,530 B2Granted
Performing a cyclic redundancy checksum operation responsive to a user-level instruction
AssigneeIntel Corporation
InventorsSteven R. King, Frank L. Berry, Michael E. Kounavis
Life of this patent
Estimating the term…
Abstract
In one embodiment, the present invention includes a method for receiving incoming data in a processor and performing a checksum operation on the incoming data in the processor pursuant to a user-level instruction for the checksum operation. For example, a cyclic redundancy checksum may be computed in the processor itself responsive to the user-level instruction. Other embodiments are described and claimed.
Claims20
A processor comprising:
- a plurality of cores, wherein at least one of the cores comprises:
- a cache;
- a plurality of general-purpose registers;
- and
- a plurality of execution units, including an integer execution unit and a single instruction multiple data (SIMD) execution unit, wherein at least one of the plurality of execution units comprises circuitry to:
- perform a cyclic redundancy check (CRC) operation in response to one or more instructions executed in a 64-bit mode of operation, wherein the circuitry is to perform the CRC operation based on one of a plurality of data sizes, including a data size of 8-bits, 16-bits, 32-bits, and 64-bits, and wherein the one or more instructions are to indicate the data size to be used.
3 more elements
A system comprising:
- a memory controller;
- a graphics engine;
- and
- a multicore processor coupled to the memory controller and the graphics engine, the multicore processor comprising a plurality of cores, wherein at least one of the cores comprises:
- a cache;
- a plurality of general-purpose registers;
- and
- a plurality of execution units, including an integer execution unit and a single instruction multiple data (SIMD) execution unit, wherein at least one of the plurality of execution units comprises circuitry to:
- perform a cyclic redundancy check (CRC) operation in response to one or more instructions executed in a 64-bit mode of operation, wherein the circuitry is to perform the CRC operation based on one of a plurality of data sizes, including a data size of 8-bits, 16-bits, 32-bits, and 64-bits, and wherein the one or more instructions are to indicate the data size to be used.
6 more elements
A system comprising:
- a main memory;
- and
- a multicore processor coupled to the main memory, the multicore processor comprising a plurality of cores, wherein at least one of the cores comprises:
- a cache;
- a plurality of general-purpose registers;
- and
- a plurality of execution units, including an integer execution unit and a single instruction multiple data (SIMD) execution unit, wherein at least one of the plurality of execution units comprises circuitry to:
- perform a cyclic redundancy check (CRC) operation in response to one or more instructions executed in a 64-bit mode of operation, wherein the circuitry is to perform the CRC operation based on one of a plurality of data sizes, including a data size of 8-bits, 16-bits, 32-bits, and 64-bits, and wherein the one or more instructions are to indicate the data size to be used.
5 more elements
Dependencies are inferred from the claim text.