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US 11,899,520 B2Granted
Dynamic cache bypass for power savings
AssigneesAdvanced Micro Devices, Inc., ATI Technologies ULC
InventorsAshish Jain, Benjamin Tsien, Chintan S. Patel, Vydhyanathan Kalyanasundharam, Shang Yang
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Abstract
A technique for operating a cache is disclosed. The technique includes in response to a power down trigger that indicates that the cache effectiveness is considered to be low, powering down the cache.
Claims20
A method for operating a cache, the method comprising:
- in response to a power down trigger that indicates that the cache effectiveness is low, powering down the cache;
- and
- wherein the power down trigger that indicates that the cache effectiveness is low comprises an access pattern that includes a miss rate in the cache being above a threshold.
A system, comprising:
- a cache;
- and
- a processor configured to execute instructions that store data in the cache,
- wherein the cache is configured to power down in response to a power down trigger that indicates that the cache effectiveness is low,
- wherein the power down trigger that indicates that the cache effectiveness is low comprises an access pattern that includes a miss rate in the cache being above a threshold.
2 more elements
A system comprising:
- a processor;
- a plurality of auxiliary devices;
- and
- a cache, wherein the processor and the plurality of auxiliary devices are clients of the cache, wherein the cache is configured to power down in response to a power down trigger that indicates that the cache effectiveness is low,
- wherein the power down trigger that indicates that the cache effectiveness is low comprises an access pattern that includes a miss rate in the cache being above a threshold.
2 more elements
Dependencies are inferred from the claim text.