System and method for timing synchronization

A system for timing synchronization between two or more nodes in network architecture, the system comprising:

• timestamp hardware to generate timestamps in data;
• a physical hardware clock (PHC clock), wherein cycle counts of the PHC clock are transmitted between the PHC clock and the timestamp hardware;
• a trigger pulse generator coupled to the PHC clock, wherein cycle counts of the PHC clock are transmitted between the PHC clock and the trigger pulse generator;
• a physical layer driver (PHY driver) to process data packets and cycle counts;
• an application coupled with the PHY driver to process timestamps and sync with the PHC clock;
• a PHC synchronizer to synchronize the PHC clock with system time;
• and
• a microprocessor coupled to the trigger pulse generator, wherein a pulse generated from the trigger pulse generator is transmitted from the trigger pulse generator to the microprocessor;
• wherein the pulse transmitted from the trigger pulse generator to the microprocessor is based on a trigger interrupt at a trigger generator interrupt time.

A system for timing synchronization between two or more nodes in network architecture, the system comprising:

• a master clock;
• a switch coupled the master clock via a first link, the switch comprising a boundary clock;
• a physical layer chip (PHY chip) coupled with the switch via a second link, wherein precision timing protocol (PTP) packets are transmitted across the second link between the switch and the PHY chip, and the PHY chip further comprises:
• PTP timestamp hardware;
• a physical hardware clock (PHC clock) coupled to the PTP timestamp hardware via a third link, wherein cycle counts are transmitted across the third link between the PHC clock and the PTP timestamp hardware;
• a trigger pulse generator coupled to the PHC clock via a fourth link, wherein cycle counts are transmitted across the fourth link between the PHC clock and the trigger pulse generator;
• a system on a chip (SOC) coupled to the PHY chip, wherein the SOC includes:
• a physical layer driver (PHY driver) to process PTP packets and cycle counts;
• a PTP application coupled with the PHY driver to process timestamps and sync with the PHC clock;
• a PHC synchronizer to synchronize the PHC clock with system time;
• a field programmable gate array (FPGA) coupled to the trigger pulse generator via a fifth link, wherein a pulse generated from the trigger pulse generator is transmitted across the fifth link from the trigger pulse generator to the FPGA;
• a sixth link between PTP timestamp hardware and the PHY driver to transmit timestamps across the sixth link between the PTP timestamp hardware and the PHY driver;
• a seventh link between the PHY clock and the PHY driver to transmit cycle counts across the seventh link between the PHC clock and the PHY driver;
• an eighth link between the trigger pulse generator and the PHY driver to transmit a trigger interrupt between and a trigger generator amount or time across the eighth link between the trigger pulse generator and the PHY driver;
• and
• wherein the pulse transmitted from the trigger pulse generator to the FPGA is based on the trigger interrupt at the trigger generator amount or time.