# US 11,899,082 B2 · Silicon hall sensor with low offset and drift compensation coils > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 11,899,082 B2 - Document ID: US11899082B2 - Status: Granted - Kind: B2 - Application number: 17/015,327 - Filed: 2020-09-09 - Published: 2022-03-10 - Granted: 2024-02-13 - Earliest claimed: 2020-09-09 - Assignees: Texas Instruments Incorporated - Applicants: Texas Instruments Incorporated - Inventors: Keith Ryan Green; Tony Ray Larson - Web page: https://patentgrep.com/patent/US11899082B2 ## CPC - G01R 33/0017: {Means for compensating offset magnetic fields or the magnetic flux to be measured; Means for generating calibration magnetic fields} - G01R 33/072: {Constructional adaptation of the sensor to specific applications} - G01R 33/0052: {Manufacturing aspects; Manufacturing of single devices, i.e. of semiconductor magnetic sensor chips (devices based on galvano-magnetic effect or the like H10N50/85)} - G01R 33/07: Hall effect devices - H10B 61/00: Magnetic memory devices, e.g. magnetoresistive RAM [MRAM] devices - H10N 52/101: {Semiconductor Hall-effect devices} - H10N 52/80: Constructional details - H10N 59/00: Integrated devices, or assemblies of multiple devices, comprising at least one galvanomagnetic or Hall-effect element covered by groups H10N50/00 - H10N52/00 (MRAM devices H10B61/00) - G01R 33/0094: {Sensor arrays} - H10N 52/01: Manufacture or treatment - G01R: MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES (indicating correct tuning of resonant circuits H03J3/12) - H10B: ELECTRONIC MEMORY DEVICES - H10N: ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR ## Abstract An integrated circuit includes a doped region having a first conductivity type formed in a semiconductor substrate having a second conductivity type. A dielectric layer is located between the doped region and a surface plane of the semiconductor substrate, and a polysilicon layer is located over the dielectric layer. First, second, third and fourth terminals are connected to the doped region, the first and third terminals defining a conductive path through the doped region and the second and fourth terminals defining a second conductive path through the doped region, the second path intersecting the first path. ## Claims ### Claim 1 An electronic device, comprising: first and second doped regions both having a first conductivity type formed in a semiconductor substrate having a second conductivity type; a dielectric layer between the first and second doped regions and a surface plane of the semiconductor substrate; first, second, third and fourth terminals connected to the first doped region, the first and third terminals defining a first conductive path through the first doped region and the second and fourth terminals defining a second conductive path through the first doped region, the second conductive path intersecting the first conductive path; a first coil formed in an interconnect level over the first doped region, and a second coil formed in the interconnect level over the second doped region; a well region having the second conductivity type laterally between the first doped region and the semiconductor substrate and bounding a perimeter of the first doped region; and a control circuit configured to produce a current that when flowing produces: a first magnetic moment by the first coil, the first magnetic moment having a normal component with a first direction with respect to the surface plane; and a second magnetic moment by the second coil, the second magnetic moment having a normal component with a second opposite direction with respect to the surface plane. ### Claim 2 (depends on 1) The electronic device of claim 1, further comprising a polysilicon layer over the dielectric layer. ### Claim 3 (depends on 2) The electronic device of claim 2, further comprising a nitrogen-containing dielectric layer over the polysilicon layer. ### Claim 4 (depends on 2) The electronic device of claim 2, further comprising openings in the polysilicon layer, each terminal making a conductive connection to the first doped region through a corresponding one of the openings. ### Claim 5 (depends on 1) The electronic device of claim 1, wherein the first coil includes a spiral structure at each of a plurality of interconnect levels. ### Claim 6 (depends on 2) The electronic device of claim 2, further comprising a transistor extending into the semiconductor substrate, the transistor having a gate electrode formed from a same material layer as the polysilicon layer. ### Claim 7 (depends on 2) The electronic device of claim 2, wherein the polysilicon layer has a lateral boundary located over the well region. ### Claim 8 (depends on 1) The electronic device of claim 1, wherein the first conductivity type is N-type and the second conductivity type is P-type. ### Claim 9 A method of forming an electronic device, comprising: forming first and second doped regions having a first conductivity type in a semiconductor substrate having a second conductivity type; forming a dielectric layer between the first and second doped regions and a surface plane of the semiconductor substrate; forming first, second, third and fourth terminals connected to the first doped region, the first and third terminals defining a first conductive path through the first doped region and second and fourth terminals defining a second conductive path through the first doped region, the second conductive path intersecting the first conductive path; forming a first coil formed in an interconnect level over the first doped region, and a second coil formed in the interconnect level over the second doped region; forming a well region having the second conductivity type located laterally between the first doped region and the semiconductor substrate and bounding a perimeter of the first doped region; and forming a control circuit configured to produce a current that causes a first magnetic moment by the first coil and a second magnetic moment by the second coil, the first magnetic moment having a normal component with a first direction with respect to the surface plane, and the second magnetic moment having a normal component with a second opposite direction with respect to the surface plane. ### Claim 10 (depends on 9) The method of claim 9, wherein the first coil includes a spiral structure at each of a plurality of interconnect levels. ### Claim 11 (depends on 9) The method of claim 9, wherein the first conductivity type is N-type and the second conductivity type is P-type. ### Claim 12 (depends on 9) The method of claim 9, further comprising forming a polysilicon layer over the dielectric layer. ### Claim 13 (depends on 12) The method of claim 12, further comprising a forming a nitrogen-containing dielectric layer over the polysilicon layer. ### Claim 14 (depends on 12) The method of claim 12, further comprising forming openings in the polysilicon layer, each terminal making a conductive connection to the first doped region through a corresponding one of the openings. ### Claim 15 (depends on 12) The method of claim 12, further comprising a forming a gate electrode of a transistor extending into the semiconductor substrate from a same material layer as the polysilicon layer. ### Claim 16 (depends on 12) The method of claim 12, wherein the polysilicon layer has a lateral boundary located over the well region. ### Claim 17 An integrated circuit, comprising: first and second doped regions both having a first conductivity type formed in a semiconductor substrate having a second conductivity type; first, second, third and fourth terminals connected to the first doped region, the first and third terminals defining a first conductive path through the first doped region and the second and fourth terminals defining a second conductive path through the first doped region, the second conductive path intersecting the first conductive path; fifth, sixth, seventh and eighth terminals connected to the second doped region, the fifth and seventh terminals defining a third conductive path through the second doped region and the sixth and eighth terminals defining a fourth conductive path through the second doped region, the fourth conductive path intersecting the third conductive path; a first coil over the first doped region, and a second coil over the second doped region, the first coil configured to direct a current over the first doped region in a clockwise direction, and the second coil configured to direct the current over the second doped region in a counterclockwise direction; and a shallow trench isolation layer between the first doped region and a surface plane of the semiconductor substrate. ### Claim 18 (depends on 17) The integrated circuit of claim 17, further comprising a current bus having a first current path configured to direct a current in a first direction and a second current path configured to direct the current in an opposite second direction, the first and second doped regions located between the first current path and the second current path. ### Claim 19 (depends on 17) The integrated circuit of claim 17, further comprising: a third doped region having the first conductivity type formed in the semiconductor substrate; a third coil over the third doped region, the third coil configured to direct the current over the third doped region in the clockwise direction; and a control circuit configured to sense a first voltage across the first doped region in a first direction, and to sense a second across the second doped region in an orthogonal second direction. ### Claim 20 An electronic device, comprising: first and second doped regions both having a first conductivity type formed in a semiconductor substrate having a second conductivity type; a dielectric layer between the first and second doped regions and a surface plane of the semiconductor substrate; a polysilicon layer over the dielectric layer; first, second, third and fourth terminals connected to the first doped region, the first and third terminals defining a first conductive path through the first doped region and the second and fourth terminals defining a second conductive path through the first doped region, the second conductive path intersecting the first conductive path; a first coil formed in an interconnect level over the first doped region, and a second coil formed in the interconnect level over the second doped region; openings in the polysilicon layer, each terminal making a conductive connection to the first doped region through a corresponding one of the openings; and a control circuit configured to produce a current that when flowing produces: a first magnetic moment by the first coil, the first magnetic moment having a normal component with a first direction with respect to the surface plane; and a second magnetic moment by the second coil, the second magnetic moment having a normal component with a second opposite direction with respect to the surface plane. ### Claim 21 An electronic device, comprising: first and second doped regions both having a first conductivity type formed in a semiconductor substrate having a second conductivity type; a dielectric layer between the first and second doped regions and a surface plane of the semiconductor substrate; a polysilicon layer over the dielectric layer; first, second, third and fourth terminals connected to the first doped region, the first and third terminals defining a first conductive path through the first doped region and the second and fourth terminals defining a second conductive path through the first doped region, the second conductive path intersecting the first conductive path; a first coil formed in an interconnect level over the first doped region, and a second coil formed in the interconnect level over the second doped region; a transistor formed extending into the semiconductor substrate, the transistor having a gate electrode formed from a same material layer as the polysilicon layer; and a control circuit configured to produce a current that when flowing produces: a first magnetic moment by the first coil, the first magnetic moment having a normal component with a first direction with respect to the surface plane; and a second magnetic moment by the second coil, the second magnetic moment having a normal component with a second opposite direction with respect to the surface plane. ### Claim 22 A method of forming an electronic device, comprising: forming first and second doped regions having a first conductivity type in a semiconductor substrate having a second conductivity type; forming a dielectric layer between the first and second doped regions and a surface plane of the semiconductor substrate; forming a polysilicon layer over the dielectric layer; forming first, second, third and fourth terminals connected to the first doped region, the first and third terminals defining a first conductive path through the first doped region and second and fourth terminals defining a second conductive path through the first doped region, the second conductive path intersecting the first conductive path; forming a first coil formed in an interconnect level over the first doped region, and a second coil formed in the interconnect level over the second doped region; forming openings in the polysilicon layer, each terminal making a conductive connection to the first doped region through a corresponding one of the openings; and forming a control circuit configured to produce a current that causes a first magnetic moment by the first coil and a second magnetic moment by the second coil, the first magnetic moment having a normal component with a first direction with respect to the surface plane, and the second magnetic moment having a normal component with a second opposite direction with respect to the surface plane. ### Claim 23 A method of forming an electronic device, comprising: forming first and second doped regions having a first conductivity type in a semiconductor substrate having a second conductivity type; forming a dielectric layer between the first and second doped regions and a surface plane of the semiconductor substrate; forming a polysilicon layer over the dielectric layer; forming first, second, third and fourth terminals connected to the first doped region, the first and third terminals defining a first conductive path through the first doped region and second and fourth terminals defining a second conductive path through the first doped region, the second conductive path intersecting the first conductive path; forming a first coil formed in an interconnect level over the first doped region, and a second coil formed in the interconnect level over the second doped region; forming a control circuit configured to produce a current that causes a first magnetic moment by the first coil and a second magnetic moment by the second coil, the first magnetic moment having a normal component with a first direction with respect to the surface plane, and the second magnetic moment having a normal component with a second opposite direction with respect to the surface plane; and forming a gate electrode of a transistor, the transistor extending into the semiconductor substrate and the gate electrode formed from a same material layer as the polysilicon layer. ### Claim 24 An integrated circuit, comprising: first and second doped regions both having a first conductivity type formed in a semiconductor substrate having a second conductivity type; first, second, third and fourth terminals connected to the first doped region, the first and third terminals defining a first conductive path through the first doped region and the second and fourth terminals defining a second conductive path through the first doped region, the second conductive path intersecting the first conductive path; fifth, sixth, seventh and eighth terminals connected to the second doped region, the fifth and seventh terminals defining a third conductive path through the second doped region and the sixth and eighth terminals defining a fourth conductive path through the second doped region, the fourth conductive path intersecting the third conductive path; a first coil over the first doped region, and a second coil over the second doped region, the first coil configured to direct a current over the first doped region in a clockwise direction, and the second coil configured to direct the current over the second doped region in a counterclockwise direction; and a current bus having a first current path configured to direct a current in a first direction and a second current path configured to direct the current in an opposite second direction, the first and second doped regions located between the first current path and the second current path. ### Claim 25 An integrated circuit, comprising: first and second doped regions both having a first conductivity type formed in a semiconductor substrate having a second conductivity type; first, second, third and fourth terminals connected to the first doped region, the first and third terminals defining a first conductive path through the first doped region and the second and fourth terminals defining a second conductive path through the first doped region, the second conductive path intersecting the first conductive path; fifth, sixth, seventh and eighth terminals connected to the second doped region, the fifth and seventh terminals defining a third conductive path through the second doped region and the sixth and eighth terminals defining a fourth conductive path through the second doped region, the fourth conductive path intersecting the third conductive path; a first coil over the first doped region, and a second coil over the second doped region, the first coil configured to direct a current over the first doped region in a clockwise direction, and the second coil configured to direct the current over the second doped region in a counterclockwise direction; a third doped region having the first conductivity type formed in the semiconductor substrate; a third coil over the third doped region, the third coil configured to direct the current over the third doped region in the clockwise direction; and a control circuit configured to sense a first voltage across the first doped region in a first direction, and to sense a second across the second doped region in an orthogonal second direction.