Testing circuit, system and control method for multiple submodules of cascaded converter

A testing system for SMs of a cascaded converter, comprising:

• a current generator, a testing module group, a cascaded converter system parameter model, a current controller, and a voltage controller;
• wherein
• the current generator is used to provide a testing current, with a specific waveform, to the testing module group;
• the testing module group comprises a plurality of testing arms, each of the plurality of testing arms comprises a plurality of tested SMs connected in series, and the plurality of testing arms are in a reverse series connection structure, in which DC voltage components in capacitor voltages of the plurality of tested SMs of the plurality of testing arms are equal in magnitude but opposite in direction;
• or
• the testing module group comprises one or more tested units, and each testing unit comprises two tested SMs in a reverse series connection, in which DC voltage components in capacitor voltages of the two tested SMs are equal in magnitude but opposite in direction, and the one or more tested units are in series relationship;
• when the testing module group receives the testing current regulated by the current generator, the testing module group outputs voltage signals of the two tested SMs;
• the cascaded converter system parameter model is used to output a reference current signal and a reference voltage signal, corresponding to system parameters and operating conditions of an actual cascaded converter, to the current controller and voltage controller;
• the current controller is used to control the testing current generated by the current generator and the current controller is used to generate control signals required by the current generator;
• and
• the voltage controller is used to control a capacitor voltage of the plurality of tested SMs in the testing module group, and to generate switching signals of the plurality of tested SMs in the testing module group,
• wherein the voltage controller, based on capacitor voltage signals of the plurality of tested SMs output by the testing module group and the reference voltage signal output by the cascaded converter system parameter model, generates control signals of switching devices in each tested SM, wherein the capacitor voltage of the each tested SM within the testing module group remains balanced, and the capacitor voltage of the each tested SM is identical to a capacitor voltage of a targeted SM in the actual cascaded converter,
• wherein the voltage controller comprises:
• a capacitor voltage balancing module and a switching signal modulation module;
• wherein:
• the capacitor voltage balancing module generates target voltage signals of the plurality of tested SMs based on the testing current output by the current generator, the capacitor voltage of the each tested SM inside the testing module group, and the reference voltage signal output by the cascaded converter system parameter model;
• wherein the reference voltage signal comprises an average capacitor voltage and a reference voltage of SM;
• the switching signal modulation module determines a number of tested SMs to be inserted according to a target voltage signal generated by the capacitor voltage balancing module, and the switching signal modulation module determines a switching status of the each tested SM according to the testing current output by the current generator.

A current control method for a cascaded converter SM testing system, wherein the current control method is used to suppress an interference of a pulse voltage output of a tested SM caused by a nearest level control (NLC) modulation on a current output waveform;

• wherein by compensating a feedforward voltage in a current controller, the interference of the pulse voltage of the tested SM caused by the NLC modulation is eliminated;
• wherein:
• the feedforward voltage used for compensation is generated by any of the following methods:
• a first method:
• calculating a difference between an inserted number of tested SMs in an inverting mode and the tested SMs in a rectifying mode, and generating the feedforward voltage in combination with a capacitor voltage of a single SM;
• a second method:
• sampling a terminal pulse voltage signal of the tested SM through a voltage sampler;
• performing a low-pass filtering on the sampled voltage signal to remove a sampling error caused by a switching dead zone;
• using a filtered voltage signal as the feedforward voltage;
• the feedforward voltage changing synchronously with the pulse voltage at a terminal of the tested SM is compensated to an output of a proportional integral and resonant (PIR) regulator in the current controller to eliminate the interference caused by the pulse voltage at the terminal of the tested SM and remove a current distortion caused by the interference of the pulse voltage.