Method for identifying latch-up structure
AssigneeChangxin Memory Technologies, Inc.
InventorQian Xu
Life of this patent
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AssigneeChangxin Memory Technologies, Inc.
InventorQian Xu
Estimating the term…
A method for identifying a latch-up structure includes the following: in a chip layout, a first N-type heavily doped region connected to a first input/output pad and located in a P-type substrate is found; a first P-type heavily doped region located in an N-well and a second P-type heavily doped region located in the P-type substrate, both of which are adjacent to the first N-type heavily doped region, are found; a second N-type heavily doped region adjacent to the first P-type heavily doped region and located in the N-well is found, wherein the N-well is located on the P-type substrate; and an area formed by the first P-type heavily doped region, the first N-type heavily doped region, the second P-type heavily doped region, the second N-type heavily doped region, the N-well and the P-type substrate is identified as the latch-up structure.
A method for identifying a latch-up structure, comprising:
A method for identifying a latch-up structure, comprising:
A method for identifying a latch-up structure, comprising:
Dependencies are inferred from the claim text.