Resistive memory cell with switching layer comprising one or more dopants

A method for forming an integrated chip, the method comprising:

• forming a bottom electrode over a substrate;
• forming a first switching layer over the bottom electrode, wherein the first switching layer comprises one or more intrinsic conductive filaments that extend from a bottom surface of the first switching layer to a top surface of the first switching layer;
• forming a second switching layer on the top surface of the first switching layer, wherein the one or more intrinsic conductive filaments are disposed in the first switching layer before forming the second switching layer;
• and
• forming a top electrode over the second switching layer.

A method for forming a memory device, the method comprising:

• forming a bottom electrode over a substrate;
• forming a lower switching layer over the bottom electrode such that the lower switching layer comprises a dielectric material co-doped with a first dopant and a second dopant, wherein a first atomic percentage of the first dopant in the lower switching layer is different from a second atomic percentage of the second dopant in the lower switching layer;
• depositing an upper switching layer over the lower switching layer;
• forming a top electrode over the upper switching layer;
• and
• patterning the lower switching layer, the upper switching layer, and the top electrode, thereby forming a memory cell.