Back to results
US 11,895,851 B2Granted
Cross point array architecture for multiple decks
AssigneeMicron Technology, Inc.
InventorsAgostino Pirovano, Lorenzo Fratin
Life of this patent
Estimating the term…
Abstract
Methods, systems, and devices for cross point array architecture for multiple decks are described. A memory array may include multiple decks, such as six or eight decks. The memory array may also include sockets for coupling access lines with associated decoders. The sockets may be included in sub-blocks of the array. A sub-block may be configured to include sockets for multiple access lines. A socket may intersect an access line in the middle of the access line, or at an end of the access line. Sub-blocks containing sockets for an access line may be separated by a period based on the access line.
Claims30
An apparatus, comprising:
- a memory array having a plurality of decks and a plurality of bit lines, each of the plurality of bit lines coupled with one or more decks of the plurality of decks, the plurality of bit lines comprising a first bit line, a second bit line, and a third bit line;
- a plurality of bit line decoders positioned beneath the memory array;
- and
- a plurality of bit line sockets comprising a first subset of bit line sockets that are arranged according to a first periodicity and couple respective segments of the first bit line with respective bit line decoders of the plurality of bit line decoders, a second subset of bit line sockets that are arranged according to a second periodicity and couple respective segments of the second bit line with respective bit line decoders of the plurality of bit line decoders, and a third subset of bit line sockets that are arranged according to the second periodicity and couple respective segments of the third bit line with respective bit line decoders of the plurality of bit line decoders.
1 more element
An apparatus, comprising:
- a plurality of tiles of a memory array, each tile of the plurality of tiles comprising a plurality of sub-blocks and a plurality of decks, wherein each sub-block of the plurality of sub-blocks comprises a plurality of memory cells of the memory array addressable via a plurality of word lines and a plurality of bit lines, each of the plurality of bit lines coupled with one or more decks of the plurality of decks, the plurality of bit lines comprising a first bit line, a second bit line, and a third bit line;
- and
- a plurality of bit line decoders positioned beneath the memory array, wherein a first bit line decoder of the plurality of bit line decoders is coupled with the first bit line using a first configuration of sockets within a first subset of the plurality of sub-blocks, a second bit line decoder of the plurality of bit line decoders is coupled with the second bit line using a second configuration of sockets within a second subset of the plurality of sub-blocks, and a third bit line decoder of the plurality of bit line decoders is coupled with the third bit line using a third configuration of sockets within a third subset of the plurality of sub-blocks.
A method, comprising:
- identifying at least one cell of a memory array, the memory array having a plurality of decks, a plurality of word lines, a plurality of word line decoders, a plurality of bit lines, and a plurality of bit line decoders positioned beneath the memory array, each of the plurality of bit lines coupled with a respective one or more decks of the plurality of decks, the plurality of bit lines comprising a first bit line, a second bit line, and a third bit line;
- and
- accessing the at least one cell of the memory array using one of the plurality of word line decoders and one of the plurality of bit line decoders, wherein the each of the plurality of bit lines are coupled with a respective bit line decoder using a plurality of bit line sockets, wherein the plurality of bit line sockets comprises a first subset of bit line sockets that are arranged according to a first periodicity and couple respective segments of the first bit line with respective bit line decoders of the plurality of bit line decoders, a second subset of bit line sockets that are arranged according to a second periodicity and couple respective segments of the second bit line with respective bit line decoders of the plurality of bit line decoders, and a third subset of bit line sockets that are arranged according to the second periodicity and couple respective segments of the third bit line with respective bit line decoders of the plurality of bit line decoders.
A method, comprising:
- identifying at least one cell of a memory array, the memory array comprising a plurality of tiles each tile of the plurality of tiles comprising a plurality of sub-blocks and a plurality of decks, wherein each sub-block of the plurality of sub-blocks comprises a plurality of memory cells of the memory array addressable via a plurality of word lines and a plurality of bit lines, the plurality of bit lines comprising a first bit line coupled with a first deck and a second deck of the plurality of decks, a second bit line coupled with a third deck and a fourth deck of the plurality of decks, and a third bit line coupled with a fifth deck and a sixth deck of the plurality of decks;
- and
- accessing the at least one cell of the memory array using a plurality of bit line decoders positioned beneath the memory array wherein a first bit line decoder of the plurality of bit line decoders is coupled with the first bit line using a first configuration of sockets within a first subset of the plurality of sub-blocks, a second bit line decoder of the plurality of bit line decoders is coupled with the second bit line using a second configuration of sockets within a second subset of the plurality of sub-blocks, and a third bit line decoder of the plurality of bit line decoders is coupled with the third bit line using a third configuration of sockets within a third subset of the plurality of sub-blocks.
Dependencies are inferred from the claim text.