US 11,895,846 B2 · Double-gated ferroelectric field-effect transistor

Abstract

A ferroelectric field-effect transistor (FeFET) includes first and second gate electrodes, source and drain regions, a semiconductor region between and physically connecting the source and drain regions, a first gate dielectric between the semiconductor region and the first gate electrode, and a second gate dielectric between the semiconductor region and the second gate electrode. The first gate dielectric includes a ferroelectric dielectric. In an embodiment, a memory cell includes this FeFET, with the first gate electrode being electrically connected to a wordline and the drain region being electrically connected to a bitline. In another embodiment, a memory array includes wordlines extending in a first direction, bitlines extending in a second direction, and a plurality of such memory cells at crossing regions of the wordlines and the bitlines. In each memory cell, the wordline is a corresponding one of the wordlines and the bitline is a corresponding one of the bitlines.

Claims25

Dependent claims

A ferroelectric field-effect transistor (FeFET), comprising:

first and second gate electrodes;
source and drain regions;
a region between and physically connecting the source and drain regions, the region comprising semiconductor material;
a first gate dielectric between the region and the first gate electrode, the first gate dielectric comprising a ferroelectric dielectric, and the first gate dielectric having a first lateral width;
and
a second gate dielectric between the region and the second gate electrode, the second gate dielectric having a second lateral width, the second lateral width different than the first lateral width.

3 more elements

Dependencies are inferred from the claim text.

Double-gated ferroelectric field-effect transistor

Life of this patent

Double-gated ferroelectric field-effect transistor

Life of this patent

Abstract

Claims25