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US 11,895,844 B2Granted
Semiconductor memory device
AssigneeKioxia Corporation
InventorGenki Kawaguchi
Life of this patent
Estimating the term…
Abstract
A semiconductor memory device according to an embodiment includes a substrate including block areas, members, conductive layers, and pillars. Each of the members is respectively disposed at a boundary portion between the block areas. At least one member of the members includes first portions and a second portion. The first portions are arranged in a first direction. The second portion is disposed between any two adjacent ones of the first portions. Either one of one of the first portions and the second portion of the member is referred to as a third portion. The other one of the one of the first portions and the second portion of the member is referred to as a fourth portion. The third portion has a width in a second direction greater than a width of the fourth portion in the second direction.
Claims15
A semiconductor memory device comprising:
- a substrate including a plurality of block areas, each of the plurality of block areas being provided to extend in a first direction, and the plurality of block areas being arranged in a second direction that intersects the first direction;
- a plurality of members, each of the plurality of members being provided to extend in the first direction, and being respectively disposed at a boundary portion between the plurality of block areas;
- a plurality of conductive layers partitioned by the plurality of members, the plurality of conductive layers being arranged in a third direction that intersects the first direction and the second direction, and being disposed separately from each other;
- and
- a plurality of pillars disposed in each of the plurality of block areas, each of the plurality of pillars being provided to penetrate the plurality of conductive layers, a portion at which one of the plurality of pillars and one of the plurality of conductive layers intersect functioning as a memory cell,
- wherein at least one member of the plurality of members includes a plurality of first portions and a second portion, the plurality of first portions being arranged in the first direction, and the second portion being disposed between any two adjacent ones of the plurality of first portions,
- when either one of one of the plurality of first portions and the second portion of the one member is referred to as a third portion, and the other one of the one of the plurality of first portions and the second portion of the one member is referred to as a fourth portion, the third portion has a width in the second direction greater than a width of the fourth portion in the second direction, and the third portion has a length in the first direction greater than the width of the fourth portion in the second direction,
- the plurality of first portions of the member have a same layer structure as the second portion,
- the fourth portion of the member includes a seam,
- the third portion of the member includes a void,
- the one member includes a contact and an insulating film, the contact including a portion provided to extend in the first direction, and the insulating film being provided between the contact and the plurality of conductive layers, and
- the contact includes the seam.
9 more elements
A semiconductor memory device comprising:
- a substrate including a plurality of block areas, each of the plurality of block areas being provided to extend in a first direction, and the plurality of block areas being arranged in a second direction that intersects the first direction;
- a plurality of members, each of the plurality of members being provided to extend in the first direction, and being respectively disposed at a boundary portion between the plurality of block areas;
- a plurality of conductive layers partitioned by the plurality of members, the plurality of conductive layers being arranged in a third direction that intersects the first direction and the second direction, and being disposed separately from each other;
- and
- a plurality of pillars disposed in each of the plurality of block areas, each of the plurality of pillars being provided to penetrate the plurality of conductive layers, a portion at which one of the plurality of pillars and one of the plurality of conductive layers intersect functioning as a memory cell,
- wherein at least one member of the plurality of members includes a first portion and a second portion arranged in the first direction,
- when either one of one of the first portion and the second portion of the one member is referred to as a third portion, and the other one of the one of the first portion and the second portion of the one member is referred to as a fourth portion, the third portion has a width in the second direction greater than a width of the fourth portion in the second direction,
- the fourth portion of the one member includes a seam, and the third portion of the member includes a void,
- the one member includes a contact and an insulating film, the contact including a portion provided to extend in the first direction, and the insulating film being provided between the contact and the plurality of conductive layers, and
- the contact includes the seam.
7 more elements
Dependencies are inferred from the claim text.