Nonvolatile memory device having cell on periphery structure

A nonvolatile memory device having a cell over periphery (COP) structure in which peripheral circuits are disposed in a peripheral region and a memory cell array is disposed in a cell region over the peripheral region, comprising:

• a first sub memory plane;
• a second sub memory plane disposed adjacent to the first sub memory plane in a row direction;
• a first vertical contact region disposed in the cell region of the first sub memory plane and disposed closer to a first end portion than to a second end portion of the cell region in a column direction;
• a second vertical contact region disposed in the cell region of the second sub memory plane and disposed closer to the second end portion, wherein the second end portion is opposite to the first end portion in a column direction;
• a first overhead region disposed in the cell region of the first sub memory plane and adjacent to the second vertical region in the row direction;
• a second overhead region disposed in the cell region of the second sub memory plane and adjacent to the first vertical region in the row direction;
• bitlines disposed at a top portion in the vertical direction of the cell region, arranged in the row direction and extending in the column direction;
• a source line disposed at a bottom portion in the vertical direction of the cell region and extending in the column direction;
• a first page buffer region disposed under the first vertical contact region;
• a second page buffer region disposed under the second vertical contact region;
• page buffers disposed in the first page buffer region and the second page buffer region;
• bitline vertical contacts disposed in the first vertical contact region and the second contact region and extending in a vertical direction to connect the bitlines and the page buffers, respectively;
• cell channel structures disposed in a main region of the cell region, each cell channel structure including a string selection transistor, memory cells and a ground selection transistor;
• half memory blocks disposed in the first overhead region and the second overhead region, each half memory block including the cell channel structures that correspond to a half of a page, wherein a page is a unit of a read operation and a write operation;
• and
• memory blocks disposed in the cell region excluding the first vertical contact region, the second vertical contact region, the first overhead region and the second overhead region, each memory block including the cell channel structures corresponding to the page.

A nonvolatile memory device comprising:

• first metal pads disposed in a cell region;
• second metal pads disposed in a peripheral region under the cell region wherein the peripheral region is vertically connected to the cell region by the first metal pads and the second metal pads;
• a first sub memory plane;
• a second sub memory plane disposed adjacent to the first sub memory plane in a row direction;
• a first vertical contact region disposed in the cell region of the first sub memory plane, wherein the first vertical contact region is disposed closer to a first end portion of the cell region in a column direction than to a second end portion of the cell region;
• a second vertical contact region disposed in the cell region of the second sub memory plane, wherein the second vertical contact region is disposed closer to the second end portion than to the first end portion of the cell region, wherein the second end portion is opposite to the first end portion in a column direction;
• a first overhead region disposed in the cell region of the first sub memory plane and adjacent to the second vertical region in the row direction;
• a second overhead region disposed in the cell region of the second sub memory plane and adjacent to the first vertical region in the row direction;
• vertical contacts disposed in the first vertical contact region and the second contact region and extending in a vertical direction;
• and
• cell channel structures disposed in a main region of the cell region, each cell channel structure including as string selection transistor, memory cells and a ground selection transistor.