US 11,895,840 B2Granted

Memory device

AssigneeSamsung Electronics Co., Ltd.

InventorsWoosung Yang, Byungjin Lee, Bumkyu Kang, Joonsung Lim

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Abstract

A memory device includes a lower structure and a plurality of upper structures stacked on the lower structure. The lower structure includes a peripheral circuit, and an upper bonding pad disposed on a top surface of the lower structure. Each of the plurality of upper structures includes a bit line, a through via, and a lower bonding pad disposed on a bottom surface of the upper structures and connected to the through via. Each of upper structures, other than an uppermost upper structure, further includes an upper bonding pad disposed on a top surface thereof and connected to the through via. The bit line includes a gap separating a first portion of the bit line from a second portion thereof in the horizontal direction, and the through via overlaps the gap of the bit line in a plan view.

Claims20

Dependent claims

A memory device comprising:

a lower structure;
and
a plurality of upper structures stacked on the lower structure,
wherein the lower structure comprises a peripheral circuit and an upper bonding pad connected to the peripheral circuit and disposed on a top surface of the lower structure,
each of the plurality of upper structures has a bottom surface, and each of the plurality of upper structures comprises a stacked structure including a plurality of gate layers stacked in a vertical direction, a plurality of channel structures each passing through the stacked structure in the vertical direction, a bit line disposed under the stacked structure and connected to the plurality of channel structures, a through via passing through the stacked structure in the vertical direction, and a lower bonding pad disposed on the bottom surface and connected to the through via,
each of upper structures, other than an uppermost upper structure, of the plurality of upper structures further comprises a top surface and an upper bonding pad disposed on the top surface and connected to the through via,
the bit line of each of the plurality of upper structures comprises a first portion extending in a horizontal direction orthogonal to the vertical direction, a second portion extending in the horizontal direction, and a gap separating the first portion of the bit line from the second portion in the horizontal direction,
in a plan view, the through via of each of the plurality of upper structures overlaps the gap of the bit line,
a lowermost upper structure of the plurality of upper structures is stacked on the lower structure in the vertical direction so that the lower bonding pad of the lowermost upper structure contacts the upper bonding pad of the lower structure,
the plurality of upper structures comprise a first upper structure and a second upper structure stacked in the vertical direction, and
the lower bonding pad of the second upper structure contacts the upper bonding pad of the first upper structure,
wherein the first portion and the second portion of the bit line of at least one upper structure of the plurality of upper structures are not connected to the lower bonding pad of the at least one upper structure,
wherein the at least one upper structure comprises a first lower line connecting the lower bonding pad of the at least one upper structure to the through via of the at least one upper structure, and a second lower line connecting the first portion of the bit line of the at least one upper structure to the second portion of the bit line of the at least one upper structure and being disconnected from the lower bonding pad of the at least one upper structure, and
wherein a bottom surface of the first lower line of the at least one upper structure is disposed on a same plane as a bottom surface of the second lower line of the at least one upper structure.

11 more elements

A memory device comprising:

a first structure;
and
a second structure stacked on the first structure,
wherein the first structure comprises a peripheral circuit, a first upper bonding pad connected to the peripheral circuit, and a second upper bonding pad connected to the peripheral circuit,
the second structure comprises a first lower bonding pad connected to the first upper bonding pad of the first structure, a first through via connected to the first lower bonding pad of the second structure, a third upper bonding pad connected to the first through via of the second structure, a second lower bonding pad connected to the second upper bonding pad of the first structure, a first bit line connected to the second lower bonding pad of the second structure, and a memory cell array connected to the first bit line of the second structure,
the first bit line of the second structure comprises a first portion, a second portion, and a first gap between the first portion of the first bit line of the second structure and the second portion of the first bit line of the second structure, and
the first lower bonding pad of the second structure is not connected to the first portion and the second portion of the first bit line of the second structure,
wherein the first through via of the second structure passes through the memory cell array of the second structure.

5 more elements

A memory device comprising:

a first structure;
and
a second structure on the first structure,
wherein the first structure comprises a peripheral circuit, a first upper bonding pad connected to the peripheral circuit, and a second upper bonding pad connected to the peripheral circuit,
the second structure comprises a first lower bonding pad connected to the first upper bonding pad of the first structure, a first through via connected to the first lower bonding pad of the second structure, a first lower line connecting the first lower bonding pad of the second structure to the first through via of the second structure, a third upper bonding pad connected to the first through via of the second structure, a second lower bonding pad connected to the second upper bonding pad of the first structure, a first bit line connected to the second lower bonding pad of the second structure, and a memory cell array connected to the first bit line of the second structure,
the first bit line of the second structure comprises a first portion, a second portion, and a first gap between the first portion of the first bit line of the second structure and the second portion thereof, and
the first lower line of the second structure is not connected to the first portion and the second portion of the first bit line of the second structure,
wherein the second structure further comprises a second through via connected to the second lower bonding pad of the second structure, and a fourth upper bonding pad connected to the second through via,
the first bit line of the second structure further comprises a third portion and a second gap between the second portion of the first bit line of the second structure and the third portion of the first bit line, and
the second lower bonding pad of the second structure is connected to the second through via of the second structure and the second portion and the third portion of the first bit line of the second structure.

7 more elements

Dependencies are inferred from the claim text.

Facts

Application: 17/895,182Filed 25 Aug 2022 · division
Priority: KR 10-2020-000674417 Jan 2020
Published: US 2022/0406814 A122 Dec 2022
Granted: 6 Feb 2024
Term ends: Not estimatedThe source records don’t support an estimate.

Classification27 codes

H10B 43/27
With source and drain on different levels, e.g. with sloping channels: the channels comprising vertical portions, e.g. U-shaped channels
G11C 7/18
Arrangements for writing information into, or reading information out from, a digital store: bit line organisation; Bit line lay-out
H10B 41/10
Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates: characterised by the top-view layout
H10B 41/27
With source and drain on different levels, e.g. with sloping channels: the channels comprising vertical portions, e.g. U-shaped channels

Family

Application17/007,141Parent of this division · filed 31 Aug 2020
US 2022/0406814 A1Pre-grant publication · published 22 Dec 2022
US 11,450,684 B2Parent of this division
US 2021/0225867 A1Published application
US 11,895,840 B2This patent

From the US filing history. Foreign family members aren’t listed.