Anti-dishing structure for embedded memory

An integrated circuit (IC), comprising:

• a memory device, comprising:
• first and second individual source/drain regions disposed in a semiconductor substrate;
• a common source/drain region in the semiconductor substrate, laterally spaced between the first and second individual source/drain regions, wherein the common source/drain region is separated from the first individual source/drain region by a first channel region, and wherein the common source/drain region is separated from the second individual source/drain region by a second channel region;
• an erase gate electrode over the common source/drain region;
• first and second floating gate electrodes respectively over the first and second channel regions;
• first and second control gate electrodes respectively overlying the first and second floating gate electrodes;
• and
• a first select gate electrode and a second select gate electrode respectively over the first and second channel regions, and laterally spaced from the common source/drain region respectively by the first and second floating gate electrodes;
• an isolation structure extending into a top surface of the semiconductor substrate and laterally separating the memory device from a logic device, the isolation structure comprising dielectric material and having an uppermost surface and a slanted upper surface extending from the uppermost surface to an edge of the isolation structure proximate to the first and second select gate electrodes;
• and
• a dummy select gate structure made of conductive material disposed on the uppermost surface of the isolation structure, wherein an upper surface of the dummy select gate structure and an upper surface of the first select gate electrode have equal heights as measured from the top surface of the semiconductor substrate.

An integrated circuit (IC) comprising:

• a semiconductor substrate including a logic region and a memory cell region separated by an isolation structure, wherein the isolation structure extends into a top surface of the semiconductor substrate and comprises dielectric material;
• a logic device on the logic region;
• a memory device on the memory cell region, wherein the memory device includes a first select gate electrode and a first floating gate electrode that are laterally spaced apart from one another over the top surface of the semiconductor substrate, wherein the first select gate electrode and the first floating gate electrode are disposed between a common source/drain region and a first individual source/drain region that are disposed in the semiconductor substrate;
• a dummy select gate structure disposed on an uppermost surface of the isolation structure, wherein the dummy select gate structure is made of the same material as the first select gate electrode and wherein an upper surface of the dummy select gate structure and an upper surface of the first select gate electrode have equal heights as measured from the top surface of the semiconductor substrate;
• a dummy control gate structure disposed on the isolation structure, wherein the dummy control gate structure has an inner sidewall facing the memory cell region;
• a sidewall spacer along the inner sidewall of the dummy control gate structure and disposed on the isolation structure, wherein the sidewall spacer has an inner sidewall facing the memory cell region;
• and
• a boundary spacer along an outer sidewall of the dummy control gate structure, where the boundary spacer has an outer sidewall that is angled at an angle of other than ninety degrees relative to a plane corresponding to the top surface of the semiconductor substrate;
• wherein the dummy select gate structure is disposed along the inner sidewall of the sidewall spacer and disposed on the isolation structure.