Manufacturing method for memory and memory

A manufacturing method for memory, comprising:

• providing a substrate, and forming a first isolation layer and discrete bit lines on the substrate, wherein the bit lines extend along a first direction, and the first isolation layer is located on surfaces of the bit lines away from the substrate and further located between adjacent bit lines;
• removing part of the first isolation layer by a thickness to form through holes arranged in an array, wherein the through holes expose part of the surface of the bit lines, and forming an active layer filling the through holes;
• removing part of the first isolation layer to form discrete first trenches, wherein the first trenches extend along a second direction, and the second direction is different from the first direction;
• and the first trenches expose a first side face and a second side face of the active layer, the first side face and the second side face are arranged oppositely;
• forming a first dielectric layer on the first side face, and forming a second dielectric layer on the second side face, wherein a thickness of an equivalent-gate dielectric layer of the first dielectric layer is greater than a thickness of an equivalent-gate dielectric layer of the second dielectric layer;
• and
• forming word lines filling the first trenches after the first dielectric layer and the second dielectric layer are formed.

A memory, comprising:

• a substrate;
• discrete bit lines located on the substrate, wherein the bit lines extend along a first direction;
• discrete word lines located on the bit lines, wherein the word lines extend along a second direction, and the second direction is different from the first direction;
• and the word lines each has a first side wall and a second side wall opposite to each other;
• an active layer, wherein the active layer is discrete and is provided between the word lines, and the active layer is located on the bit lines;
• a first isolation layer, wherein the first isolation layer is provided between adjacent bit lines, between the bit lines and the word lines, and between discrete parts of the active layer;
• a first dielectric layer, wherein the first dielectric layer is provided between the active layer and the first side wall;
• and
• a second dielectric layer, wherein the second dielectric layer is provided between the active layer and the second side wall;
• wherein a thickness of an equivalent-gate dielectric layer of the first dielectric layer is greater than a thickness of an equivalent-gate dielectric layer of the second dielectric layer;
• the first dielectric layer is of a two-layer structure, comprising an initial first dielectric layer and an initial second dielectric layer, the initial first dielectric layer covers the first side wall, and the initial second dielectric layer covers the initial first dielectric layer;
• a material of the initial first dielectric layer comprises a high-dielectric-constant material, and a material of the initial second dielectric layer comprises silicon oxide.