Semiconductor device including integrated capacitor and vertical channel transistor and methods of forming the same
AssigneeTaiwan Semiconductor Manufacturing Company, Ltd.
InventorsYun-Feng Kao, Katherine H. Chiang
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Abstract
A semiconductor device includes an insulating base including a trench, a transistor including a gate electrode and vertical channel in the trench, and a source electrode in the insulating base outside the trench, an isolation layer on the gate electrode in the trench, and a capacitor including a trench capacitor portion that is on the isolation layer in the trench, and a stacked capacitor portion that is coupled to the source electrode of the transistor outside the trench.
Claims18
A semiconductor device, comprising:
- an insulating base including a trench;
- a transistor comprising a gate electrode, a vertical channel in the trench, a drain electrode and a source electrode;
- an isolation layer on the gate electrode in the trench;
- and
- a capacitor comprising:
- a trench capacitor portion comprising a lower conductive layer, wherein the trench capacitor portion is on the isolation layer formed within the trench;
- and
- a stacked capacitor portion comprising a plurality of stacked conductive layers, wherein the stacked capacitor portion is coupled to the source electrode of the transistor formed outside the trench.
A method of forming a semiconductor device, comprising:
- forming a trench in an insulating base;
- forming a transistor, wherein the transistor comprises a gate electrode and a vertical channel formed within the trench, and a drain electrode and a source electrode formed outside the trench;
- forming an isolation layer on the gate electrode in the trench;
- and
- forming a capacitor including a trench capacitor portion that is on the isolation layer in the trench, and a stacked capacitor portion that is coupled to the source electrode of the transistor outside the trench, wherein the forming of the capacitor comprises:
- forming a lower conductive layer on the isolation layer in the trench;
- and
- forming a plurality of stacked conductive layers outside the trench, the plurality of stacked conductive layers being coupled to the source electrode of the transistor.
A dynamic random access memory (DRAM) device comprising:
- an insulating base including a trench;
- a first memory cell comprising:
- a first transistor formed within the trench;
- and
- a first capacitor comprising:
- a first trench capacitor portion including a first lower conductive layer formed within the trench;
- a first stacked capacitor portion including a first plurality of stacked conductive layers formed outside the trench;
- a second memory cell comprising:
- a second transistor formed within the trench;
- and
- a second capacitor comprising:
- a second trench capacitor portion including a second lower conductive layer formed within the trench;
- and
- a second stacked capacitor portion including a second plurality of stacked conductive layers formed outside the trench;
- and
- an isolation layer formed within the trench and isolating the first memory cell from the second memory cell.
Dependencies are inferred from the claim text.