Memory structure and forming method thereof

Abstract

The present disclosure relates to a memory structure and a forming method thereof. The present disclosure can improve the integration density of the memory structure. The memory structure includes: a plurality of vertical transistors, where the vertical transistors include silicon pillars; a plurality of the silicon pillars are arranged in m rows and n columns; the rows extend in a first direction and the columns extend in a second direction; m bit lines extending in the first direction and electrically connected to drains of all the vertical transistors in the same row, where the drains are located below the silicon pillars; and n word lines extending in the second direction, located in the middle of the silicon pillars, and serving as gates of all the vertical transistors in the same column, where the first direction and the second direction form a non-right angle.

Dependencies are inferred from the claim text.