Implantations for forming source/drain regions of different transistors

A structure comprising:

• a semiconductor substrate;
• and
• a first transistor comprising:
• a first gate stack over the semiconductor substrate;
• a first gate spacer aside of the first gate stack;
• a first epitaxy region on a side of the first gate stack, wherein the first epitaxy region comprises:
• a first lower portion having a conductive type, wherein the first lower portion has a first doping concentration of the conductivity type;
• and
• a first upper portion having a second doping concentration of the conductivity type, wherein the second doping concentration is higher than the first doping concentrate, and wherein a first inner edge of the first upper portion is spaced apart from a first nearest outer edge of the first gate spacer;
• and
• a first source/drain silicide region over and contacting the first epitaxy region, wherein the first source/drain silicide region has a second inner edge vertically aligned to the first inner edge of the first upper portion.

A structure comprising:

• a semiconductor substrate;
• and
• a first transistor comprising:
• a first gate stack over the semiconductor substrate;
• a first gate spacer on a sidewall of the first gate stack;
• and
• a first semiconductor region aside of the first gate stack, wherein the first semiconductor region comprises silicon germanium;
• a first p-type doped region in the first semiconductor region, wherein the first p-type doped region has a p-type dopant concentration higher than p-type concentrations of portions of the first semiconductor region on opposing sides of the first p-typed doped region;
• and
• a first source/drain silicide region over and contacting the first p-type doped region, wherein the first source/drain silicide region has substantially a same width as the first p-type doped region.