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US 11,895,816 B2Granted
Bitcell architecture
AssigneeArm Limited
InventorsAmit Chhabra, Brian Tracy Cline
Life of this patent
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Abstract
Various implementations described herein are related to a device having multiple transistors that are arranged as a bitcell. The multiple transistors may include multiple P-type transistors that are arranged in a P-over-P stack configuration, and the multiple transistors may include multiple N-type transistors that are arranged in an N-over-N stack configuration.
Claims20
A device comprising:
- multiple transistors arranged as a bitcell;
- wherein the multiple transistors include multiple P-type transistors that are sequentially arranged in a P-over-P stack configuration,
- wherein the multiple transistors include multiple N-type transistors that are sequentially arranged in an N-over-N stack configuration, and
- wherein the multiple P-type transistors in the P-over-P stack configuration are disposed alongside the multiple N-type transistors in the N-over-N stack configuration.
1 more element
A bitcell comprising:
- a pair of P-type devices sequentially arranged in a P-over-P stack configuration;
- and
- a pair of N-type devices sequentially arranged in an N-over-N stack configuration,
- wherein the pair of P-type transistors in the P-over-P stack configuration is disposed alongside the pair of N-type transistors in the N-over-N stack configuration, and
- wherein the pair of P-type devices is cross-coupled with the pair of N-type devices so as to provide two cross-coupled inverters that are used as a latch for the bitcell.
2 more elements
A method comprising:
- fabricating multiple devices that are arranged as a bitcell;
- fabricating the multiple devices with a pair of P-type transistors that are sequentially arranged in a P-over-P stack configuration;
- fabricating the multiple devices with a pair of N-type transistors that are sequentially arranged in an N-over-N stack configuration;
- and
- cross-coupling the pair of P-type transistors with the pair of N-type transistors so as to provide two cross-coupled inverters that are used as a latch for the bitcell,
- wherein the pair of P-type transistors in the P-over-P stack configuration is disposed alongside the pair of N-type transistors in the N-over-N stack configuration.
3 more elements
Dependencies are inferred from the claim text.