Clock synchronization using wireless side channel

A computing device comprising:

• a data input configured to receive a master timing reference from an intermediate device over a dedicated data channel, wherein the master timing reference is generated by a master device;
• and
• timing circuitry configured to synchronize a slave timing reference to the master timing reference to a resolution within one tick of the master timing reference using a snapshot of the master timing reference transmitted over the dedicated data channel and a fixed known delay for a data packet containing the snapshot to be transmitted between the master device and the computing device via the intermediate device, the fixed known delay including an internal processing delay at the master device and transit time between the master device and the computing device, wherein the transmit time includes a constant retransmission processing delay for each hop between the master device and the computing device and a number of hops between the master device and the computing device.

A computing device comprising:

• a data input configured to receive a master timing reference from an intermediate device over a dedicated data channel, wherein the master timing reference is generated by a master device;
• and
• timing circuitry configured to synchronize a slave timing reference to the master timing reference to a resolution within one tick of the master timing reference by comparing measured crystal ticks between a series of incoming timing packets to a known packet rate of the series of incoming timing packets received over the dedicated data channel from the master device to the computing device via the intermediate device, wherein the known packet rate includes a constant retransmission processing delay for each hop between the master device and the computing device and a number of hops between the master device and the computing device.