Timing precision maintenance with reduced power during system sleep
AssigneeAnalog Devices, Inc.
InventorsBrett Warneke, Gary Wayne Ng, Mark Alan Lemkin
Life of this patent
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Abstract
Embodiments of the present disclosure provide systems and methods for maintaining timing precision in different operating modes of a device (e.g., a wireless node). A timing circuit may switch clock signals between two different modes (e.g., high power and low power) while preserving timing precision. In a high-power mode, the timing circuit may provide a high frequency clock signal, and in a lower-power mode, it may provide a low frequency clock signal. Moreover, the switching between the different clock signals may be synchronized to select edges of the low frequency clock signal.
Claims16
A clock circuit comprising:
- a clock to generate a first clock signal having a first frequency;
- a clock divider to divide the first clock signal to generate a second clock signal output at a second frequency, wherein the first frequency is higher than the second frequency;
- a multiplexor to receive the first and second clock signals as inputs;
- a controller coupled to the multiplexor to control the multiplexor to output the first clock signal during a first mode and to output the second clock signal during a second mode, wherein switching directly between the first clock signal and second clock signal by the multiplexor is performed based on a select edge of the second clock signal;
- and
- a system time counter coupled to the multiplexor to maintain a system time count, wherein the system counter configured to increment the system time count based on the first clock signal during the first mode and to increment the system time count based on the second clock signal during the second mode.
A method to maintain timing between different modes, the method comprising:
- receiving a command to switch from a first power mode to a second power mode;
- in response to receiving the command, detecting a next specified edge of a low frequency clock signal of a set of clock signals;
- switching directly to a clock signal corresponding to the second power mode at the detected edge of the low frequency clock;
- maintaining a system time count based on a second clock signal corresponding to the first power mode;
- and
- in response to switching to the clock signal corresponding to the second power mode, maintaining the system time count based on the clock signal corresponding to the second power mode.
A device to maintain timing between modes, the device comprising:
- a radio interface to communicate with another device;
- and,
- a clock circuit, comprising:
- a clock to generate a first clock signal having a first frequency;
- a clock divider to divide the first clock signal to generate a second clock signal at a second frequency, wherein the first frequency is higher than the second frequency;
- a multiplexor to receive the first and second clock signals as inputs;
- and
- a controller coupled to multiplexor to control the multiplexor to output the first clock signal during a first mode and to output the second clock signal during a second mode, wherein switching directly between the first clock signal and second clock signal by the multiplexor is performed based on a select edge of the second clock signal;
- and
- a system time counter coupled to the multiplexor to maintain a system time count, wherein the system counter configured to increment the system time count based on the first clock signal during the first mode and to increment the system time count based on the second clock signal during the second mode.
Dependencies are inferred from the claim text.