Ultra-low latency advanced encryption standard
AssigneeIntel Corporation
InventorMichael Kounavis
Life of this patent
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Abstract
In one example, an apparatus for Advanced Encryption Standard (AES) substitutions box (S-box) encryption includes an S-Box logic function and a MixColumns multiplication operation. The S-box logic function takes as input a state and is an 8-bit to 8-bit logic function, and wherein the S-box logic function is minimized such that an S-box round comprises nine not-and (NAND) levels and duplications of a logical product of the minimized S-box logic function are eliminated. The MixColumns multiplication operation comprises a plurality of factors that are exclusive ORed (XOR) with an output of the S-box round to obtain a scaled 16-byte output.
Claims25
An apparatus implementing an Advanced Encryption Standard (AES) substitutions box (S-box) encryption, comprising:
- an S-box logic function, wherein the S-box logic function takes as input a state and is an 8-bit to 8-bit logic function, and wherein the S-box logic function is minimized such that an S-box round comprises nine not-and (NAND) levels and duplications of a logical product of the minimized S-box logic function are eliminated;
- and
- a MixColumns multiplication operation, wherein the MixColumns multiplication operation comprises a plurality of factors that are exclusive ORed (XOR) with an output of the S-box round to obtain a scaled 16-byte output.
A substitution box (S-box), comprising:
- a logic function, wherein the logic function comprises input bits and substitution bits, and the logic function is expressed by nine or fewer logic levels and the total number of logic gates is within 1200 to 1250 gates.
A method for an Advanced Encryption Standard (AES) substitutions box (S-box) encryption, comprising:
- receiving as input a state by an S-box logic function, wherein the S-box logic function is an 8-bit to 8-bit logic function and is minimized such that an S-box round comprises nine not-and (NAND) levels and duplications of a logical product of the minimized S-box logic function are eliminated;
- and
- performing a MixColumns multiplication operation, wherein the MixColumns multiplication operation comprises a plurality of factors that are exclusive ORed (XOR) with an output of the S-box round to obtain a scaled 16-byte output.
Dependencies are inferred from the claim text.